Static analysis-based method and system for detecting RTL (Resistor Transistor Logic) design errors

Abstract

The invention discloses a static analysis-based method and system for detecting RTL (Resistor Transistor Logic) design errors. The method comprises the following steps of: receiving an RTL design source code and a corresponding design specification file, constructing and storing a detection standard of errors to be detected according to the type of the errors to be detected and in combination with the design specification file; traversing the whole RTL design source code in modules aiming at the types of the errors to be detected, extracting characteristic information of the errors to be detected through lexical analysis, grammatical analysis and static semantic analysis, and storing the characteristic information; and judging whether the detection standard of the errors to be detected ismatched with the characteristic information, if so, ending the error detection of the design to be detected, and otherwise, sending an error report.

Description

technical field [0001] The invention relates to the field of large-scale integrated circuit design verification, in particular to a static analysis-based register transfer level (Register Transfer Level, RTL) design error detection method and system. Background technique [0002] With the development of integrated circuit (IC) technology, the degree of chip integration is further improved, the scale of the circuit becomes larger and the complexity becomes higher and higher, in order to ensure the consistency of design implementation and design specification , design verification (design verification) has become the biggest challenge in IC design. In the actual IC design process, functional verification has become a key factor and the most time-consuming link, and the growth of its processing scale and efficiency lags behind that of the design scale. Therefore, how to automate the repetitive and tedious verification process, further improve the efficiency of functional verif...

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Problems solved by technology

[0006] 1) The complexity of the functional logic of the design to be tested has increased sharply, and it is difficult to find all design errors by relying on the experience of engineers or using traditional verification methods;

[0007] 2) The sharp increase in the number of registers contained in the design under test leads to slower and slower dynamic simulation verification and makes formal verification methods more difficult to handle

[0010] The static error detection method used in IC design verification in the prior art is mainly formal verification, which mainly proves the correctness of the system through strict mathematical reasoning, but usually requires the participation of experts, and the size of its state space will vary with the design The number of registers increases exponentially, there is a "state explosion" problem, and the processing scale is small, which limits its application in large-scale design verification

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