Dual-threshold domino circuit with optimal gate control vector used in low-power consumption VLSI (very large scale integration)

A domino, dual-threshold technology, applied in logic circuits, electrical components, pulse technology, etc., to achieve the effect of reducing leakage power consumption

Inactive Publication Date: 2011-05-25
BEIJING UNIV OF TECH
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] When the dual-threshold domino circuit is placed in the dormant state, the difference in the input vector determines the tu

Method used

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  • Dual-threshold domino circuit with optimal gate control vector used in low-power consumption VLSI (very large scale integration)
  • Dual-threshold domino circuit with optimal gate control vector used in low-power consumption VLSI (very large scale integration)
  • Dual-threshold domino circuit with optimal gate control vector used in low-power consumption VLSI (very large scale integration)

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Embodiment Construction

[0020] The present invention will be further described below in conjunction with the accompanying drawings and embodiments.

[0021] This embodiment applies the optimal gating vector to a double-threshold domino OR gate.

[0022] Such as figure 2 and 3 Shown is the optimal gating vector for a dual-threshold domino OR gate, which consists of several parts:

[0023] Such as figure 2 As shown, at high temperature, including input signal terminal, output signal terminal, clock signal terminal, pre-charge tube Pg1, holding tube Pg2, clock tube Ng1, Pg3 and Ng2 in the output static inverter, and pull-down network (PDN) in NMOS transistors, wherein the NMOS transistors in the pre-charging transistor, the holding transistor and the static inverter are high-threshold transistors, and the rest of the transistors are low-threshold transistors. In sleep mode, the input is high level 1, and the clock signal is high level 1.

[0024] Such as image 3 As shown, at room temperature, i...

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Abstract

The invention relates to a dual-threshold domino circuit with an optimal gate control vector used in low-power consumption VLSI (very large scale integration), i.e., when the dual-threshold domino circuit is in a dormant state, leakage power consumption of the domino circuit is reduced by utilizing the optimal gate control vector. In the invention, after the dual-threshold domino circuit just enters the dormant state from an operating state, a chip is kept at unchanged high temperature owing to short time, and at the moment, the leakage power consumption can be effectively reduced by utilizing the gate control vector with a high-level input signal and a high-level clock signal; and after the dual-threshold domino circuit is changed into the dormant state from the operating state for a period of time, the temperature of the chip is reduced to room temperature, and at the moment, the leakage power consumption can be more effectively reduced by utilizing the gate control vector with a low-level input signal and a low-level clock signal.

Description

technical field [0001] The invention relates to a low power consumption circuit, in particular to a double threshold low power consumption domino circuit using an optimal gating vector, which belongs to the field of integrated circuit applications. Background technique [0002] Domino circuits are widely used in the critical path of processors and memories due to their excellent characteristics of fast speed and small area. They are the most mainstream dynamic logic circuits for high-performance processors and memories. The standard domino circuit is an important branch of the CMOS circuit, which is composed of a dynamic logic block composed of a group of NMOS tubes and a static inverter, such as figure 1 shown. The working principle of the circuit is as follows: when the clock signal CLK=0, it is the pre-charging stage of the circuit. At this time, the pre-charging PMOS transistor P1 is in the conduction state, and the dynamic node is pre-charged to the high level V dd , ...

Claims

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Application Information

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IPC IPC(8): H03K19/094
Inventor 汪金辉吴武臣侯立刚宫娜耿淑琴张旺袁颖
Owner BEIJING UNIV OF TECH
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