Structure and method for testing integrity of grid oxide layer and dielectric layer

Abstract

The invention relates to a structure and method for testing the integrity of a grid oxide layer and a dielectric layer. The method for testing the integrity of the grid oxide layer comprises the following steps of: testing the integrity of the grid oxide layer through a first welding pad and a second welding pad, calibrating that a test result is in a passed state and finishing the test if the test is passed; or else, testing whether a short-circuited problem exists between the first welding pad and a third welding pad or between the second welding pad and the third welding pad; calibrating that the test result is in a passed state and finishing the test if the short-circuited problem exists; and calibrating that the test result is in a failed state and finishing the test if the short-circuited problem does not exist. The invention eliminates the interference of a short-circuited problem in a metal interaction layer on the test result and improves the test accuracy in testing the integrity of the grid oxide layer and the dielectric layer.

Description

technical field [0001] The invention relates to the field of semiconductor testing, in particular to a testing structure and testing method for the integrity of a gate oxide layer and a testing structure and testing method for the integrity of a dielectric layer. Background technique [0002] In the manufacturing process of a semiconductor device, in order to monitor the manufacturing process and ensure the reliability of the semiconductor device, it is common practice to form a test structure (testkey) in the device for testing some key parameters. In the CMOS process, the gate oxide layer (gate oxide) is an important structure in the device structure. The gate oxide layer should be an ideal dielectric layer without defects affecting its insulating properties. However, in the manufacturing process such as ion diffusion intrusion , Trapped charge and other factors will affect the quality of the gate oxide layer. [0003] The gate oxide integrity (GOI for short) test is a te...

AI Technical Summary

Problems solved by technology

Therefore, if there is a defect in the metal interconnection layer 110, it will affect the test result of the gate oxide layer integrity test

If the breakdown voltage between pad 103 and pad 104 is small during the test and the test result fails, the reason may be either a defect in the gate oxide layer 101 or a defect in the metal interconnection layer 110 , if there is a bridging defect between the connection pads 110a and 110b, such as image 3 As shown, there is residual metal on the metal interconnection layer 110, causing a short circuit between the connection pads 110a and 110b, thereby causing a short circuit between the pads 103 and 104.

In the actual test process, in order to determine whether the real reason for the test failure lies in the gate oxide layer or the metal interconnection layer, a failure analysis (failure analysis, FA for short) is required, which takes a lot of time, manpower and equipment costs

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