Time-delay circuit

Abstract

The invention discloses a time-delay circuit. In the invention, a first PMOS (P-channel Metal Oxide Semiconductor) tube, a second NMOS (N-channel metal oxide semiconductor) tube, a first current source circuit, a second power supply circuit and a first capacitor form a first capacitance charge and discharge switching circuit; a third PMOS tube, a fourth NMOS tube, a third current source circuit, a fourth current source circuit and a second capacitor form a second capacitance charge and discharge switching circuit; and an input signal is output sequentially through the first capacitance charge and discharge switching circuit, a first buffer, the second capacitance charge and discharge switching circuit and a second buffer or a phase inverter. The time-delay circuit eliminates the influence of process offsets by utilizing the time delay of the two capacitance charge and discharge switching circuits to mutually compensate so as to ensure that the time delay is more precise.

Description

technical field [0001] The invention relates to a semiconductor integrated circuit, in particular to a delay circuit. Background technique [0002] Delay circuits are widely used in many integrated circuit IP (Intellectual Property). Accurate delay circuits can improve the performance of integrated circuit IP and increase the yield of wafers, especially in NVM (Non-Volatile Memory non-volatile In the field of volatile memory), a precise delay circuit can improve the reading speed of NVM. [0003] The traditional delay circuit is to directly use the delay accumulation of the inverter to generate the required delay (such as figure 1 shown), or use the reference current source to charge and discharge the capacitor with the required delay (such as figure 2 shown). Since the flipping voltage of a buffer or inverter is greatly affected by supply voltage and process variation), the figure 1 The delay circuit shown is sensitive to process variation, while the figure 2 The del...

AI Technical Summary

Problems solved by technology

Therefore, the delay produced by the traditional delay circuit has a relatively large deviation under different conditions, and the delay accuracy is not high.

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