Oxidizing-dephlegmation-based silicon-based wrap gate transistor with buried-channel structure and preparation method thereof

Abstract

The invention provides a silicon-based wrap gate transistor with a buried-channel structure, and belongs to the field of electronic semiconductor devices. The transistor comprises a channel region, a gate medium, a gate region, a source region, a drain region and a source / drain terminal epitaxial region, wherein the channel region has a silicon nanowire structure with three layers, a cylindrical channel region lower layer is arranged inside the channel region, and the channel region and the channel region upper layer are wrapped outside the channel region lower layer respectively; impurities with opposite types are mixed into the channel region upper layer and the channel region lower layer; a layer of gate medium region is covered outside the channel region upper layer; and the gate region is positioned on the outer layer of the gate medium. In a preparation method, the silicon-based wrap gate transistor with the buried-channel structure which is suitable to be applied to high-speed circuits is prepared on the basis of an oxidizing dephlegmation technology, so that the phenomena of descending in mobility and serious random telegraph noise which are caused by the polycrystal orientation of wrap gate devices are avoided.

Description

technical field [0001] The invention relates to gate-enclosed field-effect transistors in the field of microelectronic semiconductor devices, in particular to a silicon-based gate-enclosed transistor with buried trench structure suitable for high-speed and low-power consumption circuits based on oxidation segregation technology. Background technique [0002] With the continuous reduction of cost, increase of integration, and improvement of performance of VLSI, the feature size of CMOS devices is continuously reduced, and the leakage current of devices is increasing, and the short-channel effect (SCE: Short-Channel-Effect) is becoming more and more serious. In order to overcome the main problem that hinders the shrinking of the device size, one of the effective ways is to use the multi-gate structure to improve the control ability of the gate to the channel, improve the device characteristics, and make the device better adapt to the small size field. Multi-gate device structu...

AI Technical Summary

Problems solved by technology

[0003] However, an unavoidable problem of silicon-based gate-enclosed devices is the multi-orientation of the channel. The dangling bonds generated by the multi-orientation increase the density of traps and also aggravate carrier scattering and random telegraphy. Noise phenomenon (RTN: Random-Telegraph-Noise)

When carriers flow through the surface channel, the carriers will be attracted or repelled by the trapped charges, changing the transport direction, reducing the mobility of the carriers, thereby reducing the transport speed in the channel direction

At the same time, because the traps have a trapping and releasing effect on the carriers, the traps brought by the polycrystalline orientation can trap or release the carriers in the conduction current, and some traps will have a greater impact on the channel current in this process. , forming a random telegraph noise phenomenon

A certain surface roughness (surface roughness) is inevitably introduced in the process of making gate-enclosed devices, which will also lead to a decrease in the mobility of silicon-based gate-enclosed devices.

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