Low-power-consumption LDPC (low density parity check) decoder based on optimization of folding structure of memorizer

Abstract

The invention discloses a low-power-consumption LDPC (low density parity check) decoder based on optimization of a folding architecture of a memorizer, comprising an input cache, an output cache, a check node computing unit, a variable node computing unit, a memory cell, an address generation unit, a control unit and internet. The decoder is based on a part of parallel decoding structure and uses read-write rules of the memorizer in the decoding process sufficiently; and a folding architecture method is adopted to design the memory cell, thus reducing the times of read-write operations of the memorizer manyfold, thereby greatly decreasing the power consumption of the decoder. In the architecture method of the memorizer, a specific LDPC decoding algorithm is not changed, and error code performances and timing sequence of a circuit are not influenced totally, thus the architecture method can be applied to different types and different standards of LDPC decoders as well as regular and irregular types of decoders.

Description

technical field [0001] The invention relates to the technical field of channel coding and decoding in the communication field, in particular to a low-power low-density parity-check code (LDPC) decoder based on memory folding architecture optimization. Background technique [0002] In a wireless communication system, the transmission channel is inevitably affected by factors such as noise, fading, and multipath, which greatly limit the rate and quality of data transmission under a certain bandwidth. Therefore, in modern communication systems with high throughput rate, large capacity and high reliability, error control coding technology has been widely used. [0003] Low-density parity-check code (LDPC) is a very important type of code in error control coding, which was first proposed by Gallager in 1962. It has been verified that LDPC codes have performance close to the Shannon limit. At the same time, due to the structural characteristics of the parity check matrix of the L...

AI Technical Summary

Problems solved by technology

However, usually the H matrix is ​​huge and sparse, resulting in a complex structure of the LDPC decoder, a relatively large hardware resource overhead, and a large proportion of the power consumption of the entire wireless communication system.

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