Short pulse signal realization method and device

Abstract

The invention relates to a short pulse signal realization method and a short pulse signal realization device. The device comprises a latch unit, a delay unit and a resetting unit, wherein the latch unit is used for latching the high level of an input signal; the delay unit is used for delaying the latched signal; the resetting unit is used for asynchronously clearing the latched signal; the latch unit is connected to the resetting unit by the delay unit; the resetting unit is connected to the latch unit; and the latch unit is a trigger. By the short pulse signal realization method and the short pulse signal realization device, nanosecond short pulses can be generated, and the widths of the pulses are related to a delay parameter of a delay circuit and unrelated to the frequency of a working clock of the circuit, and can meet given phase relationships.

Description

technical field [0001] The invention relates to a method for realizing a pulse signal, in particular to a method for realizing a short-time pulse signal and a device thereof. Background technique [0002] At present, FPGA is widely used in the field of digital system design. FPGA-based design methods have the advantages of flexibility and high integration. However, the application of FPGA must face the constraints of device speed and area. For specific application fields such as aerospace and military industry, the available The resources and speed of FPGA are very limited. When the speed and resources are limited, the design work of FPGA will face some new problems. For example, in an FPGA design task, it is necessary to generate periodic short-time pulse control signals. The width of these pulse signals is about 10 ns. If it is realized by a conventional synchronous design method, the FPGA needs an input clock with a frequency of at least 100 MHz. However, the maximum ope...

AI Technical Summary

Problems solved by technology

[0002] At present, FPGA is widely used in the field of digital system design. FPGA-based design methods have the advantages of flexibility and high integration. However, the application of FPGA must face the constraints of device speed and area. For specific application fields such as aerospace and military industry, the available The resources and speed of FPGA are very limited. When the speed and resources are limited, the design work of FPGA will face some new problems.

For example, in a certain FPGA design task, it is necessary to generate periodic short-time pulse control signals. The width of these pulse signals is about 10ns. If it is realized by the conventional synchronous design method, the FPGA needs an input clock with a frequency of at least 100MHz. However, the maximum operating frequency of the FPGA that can be obtained by the design task is only 70MHz. Obviously, constraints limit the application of conventional methods, and a new design method is urgently needed to break through the speed limit of the FPGA device itself and generate nanosecond-level short-duration pulses and satisfy a specific phase relationship

Images