2results about How to "Implementation is flexible" patented technology

This invention relates to the field of advanced semiconductor packaging and chiplet integration technology, specifically disclosing a heterogeneous die system-on-a-chip and its fabrication method. The method includes: S1: providing an adapter board, the top surface of which is provided with a first I / O pad, and forming a first metal interconnect region above the first I / O pad, or using the first I / O pad as the first metal interconnect region; S2: providing a chiplet, the top surface of which is provided with a second I / O pad, and fabricating a second metal interconnect region on the top surface of the chiplet. This invention achieves self-aligned interconnection of the metal interconnect regions between the chiplet and the adapter board by combining an open area on the top surface of the adapter board with selective deposition, eliminating the need for high-precision photolithography alignment and significantly reducing process complexity. Simultaneously, this method supports multi-layer PAD expansion, multi-array parallel interconnection, wafer-level batch integration, and various layout methods, achieving high-density, low-latency, and high-reliability chiplet interconnection.

The invention belongs to the technical field of communication, and particularly relates to an energy consumption control method, device and equipment, a readable storage medium and a computer program product, and the method comprises the steps that an AF or a terminal sends first information to a first network element; wherein the first information comprises energy consumption threshold information; and the first network element sends the first information to a second network element, and the second network element executes related operation based on the first information according to the first information.