Wafer level packaging structure and packaging method

Abstract

A wafer-level packaging structure and packaging method, wherein the wafer-level packaging method includes: providing a wafer to be packaged, a plurality of discrete pads are formed on the surface of the wafer; forming conductive contour columns on the surface of the pads ; Form bumps on the surface of the contour column. The wafer-level packaging method provided by the invention has a simple process, and the wafer-level packaging structure provided by the invention has high packaging quality.

Description

technical field [0001] The invention relates to the field of chip packaging, in particular to a wafer-level packaging structure and packaging method. Background technique [0002] As the size of the chip becomes smaller and the function becomes stronger, the number of pads increases and the spacing becomes narrower. Correspondingly, higher requirements are put forward for the chip package. [0003] The traditional chip packaging method usually uses wire bonding (Wire Bonding) for packaging, but with the rapid development of chips, wafer-level packaging gradually replaces wire bonding. In the Chinese patent document with the publication number CN101740422A, it can be found that more More information about wafer level packaging. [0004] The existing wafer-level packaging process specifically includes: Please refer to figure 1 , providing a wafer 100 to be packaged, the surface of the wafer 100 to be packaged has a plurality of discrete pads 101 and a passivation layer 102, ...

AI Technical Summary

Problems solved by technology

[0009] However, the wafer-level packaging formed by the above process may have open circuit phenomenon, and the reliability of the packaged product is poor

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