Strain semiconductor channel formation method and semiconductor device

Abstract

A method for forming a strained semiconductor channel and a semiconductor device are provided. The method includes the following steps: forming a SiGe relaxation layer on a semiconductor substrate; forming a dielectric layer on the SiGe relaxation layer, forming a dummy gate on the dielectric layer, the dielectric layer and the dummy gate composing a dummy gate structure; depositing an inter-layer dielectric layer, planarizing the inter-layer dielectric layer to expose the dummy gate; etching and removing the dummy gate and the dielectric layer to form an opening; selectively growing a semiconductor epitaxial layer in the opening; depositing a high-K dielectric layer and a metal layer; planarizing the metal layer and the high-K dielectric layer, and then removing the high-K dielectric layer and the metal layer which cover the inter-layer dielectric layer to form a metal gate.

Description

technical field [0001] The present invention relates to the field of semiconductors, in particular to a semiconductor device and a manufacturing method thereof, and more particularly to a method for forming a strained semiconductor channel and a semiconductor device manufactured by the method. Background technique [0002] In SiGe semiconductor devices, a tensile-strained Si layer structure disposed on a SiGe relaxation layer is widely used. Usually, the composition of the SiGe relaxed layer is represented by Si 1-x Ge x In the form of x∈[0,1]. [0003] Figure 1A A schematic diagram of the atomic lattice showing the structure of a tensile strained Si layer disposed on a SiGe relaxed layer, Figure 1B The energy level structure of a tensile strained Si layer structure disposed on a SiGe relaxed layer is shown. Such as Figure 1B As shown, the conduction band in the tensile strained Si layer is lower than that in the SiGe relaxed layer due to the larger biaxial tensile s...

AI Technical Summary

Problems solved by technology

[0006] However, in conventional Si channel formation methods, strained Si must be formed on the SiGe layer (or buried oxide) prior to device fabrication processes (e.g., shallow trench isolation (STI), gate formation, etc.) cladding

This also leads to the following problems in the traditional Si channel formation method: (1) During the device manufacturing process, the strained Si capping layer may suffer loss, for example, pad oxidation treatment in STI process, sacrificial oxidation before gate formation process treatment, various wet chemical cleaning treatments, etc., may cause loss of the strained Si coating; (2) The strained Si coating may relax (stress is released) during high temperature steps, for example, for activating the source / Annealing of the drain dopant may cause the stress in the strained Si cladding to be released

Images