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Mos type semiconductor device and method of manufacturing same

A manufacturing method and semiconductor technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve the problems of difficult avalanche current concentration, difficult to ensure, narrow openings, etc., to prevent the increase of on-resistance and reduce costs Effect

Inactive Publication Date: 2012-02-08
FUJI ELECTRIC CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The narrowing of the width of the opening makes it difficult to secure a sufficient contact area with the source electrode 13 in the opening.
Therefore, it is practically difficult to make the opening narrow enough necessary to concentrate the avalanche current to the bottom of the structure

Method used

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  • Mos type semiconductor device and method of manufacturing same
  • Mos type semiconductor device and method of manufacturing same
  • Mos type semiconductor device and method of manufacturing same

Examples

Experimental program
Comparison scheme
Effect test

example 1

[0079] Figure 1(a) , 1(b) And 1(c) are cross-sectional views showing the wafer process of the MOSFET according to Example 1 of the present invention. figure 2 It is a cross-sectional view of an important part of the MOSFET according to Example 1 of the present invention. Right and Picture 9 The same parts of the conventional MOSFET described in the above are marked with the same reference numbers. Figure 1(a) , 1(b) And 1(c) is a cross-sectional view of the important part of the MOSFET in the wafer process, which is up to the step of covering the entire front surface of the gate electrode 8 and the interlayer dielectric film 10.

[0080] The following describes the case of MOSFET. The semiconductor substrate used includes: will become n + High concentration n of drain layer 2 + Silicon substrate, and in the above n + High resistance n formed by epitaxial growth on silicon substrate - Drift layer 1. An oxide film 31a is formed, and the width of the oxide film 31a is the same as...

example 2

[0090] image 3 with Figure 4 It is a cross-sectional view of an important part of a MOSFET according to Example 2 of the present invention. Right and Picture 9 The same parts are marked with the same reference numbers. image 3 This is a cross-sectional view of an important part of the MOSFET in a process state. In this process, the entire front surface including the area on the gate electrode 8 is covered with the interlayer dielectric film 10.

[0091] First, prepare a semiconductor substrate, which includes n + Drain layer 2, and at n + The high-resistance n layer formed by epitaxial growth on the drain layer 2 - Drift layer 1. Through the LOCOS process, a LOCOS oxide film 31b different from the oxide film 31a in Example 1 is formed so that the silicon surface has recesses. Using the above-mentioned oxide film 31b as a mask, an n region 32 is formed by implanting a dopant such as phosphorus. The n region 32 is shallower than the p base region 17 and the impurity concentratio...

example 3

[0096] On the back side, that is, the side opposite to the above-mentioned front side, it can be at n - The opposite side of the drift layer is separated by n + Buffer layer to form p + Collector layer, resulting in the IGBT structure. In the case of an IGBT, a parasitic thyristor appears at the position of the parasitic bipolar transistor of the MOSFET. Parasitic thyristors, like parasitic bipolar transistors in MOSFETs, can be prohibited from conducting, thereby preventing the device from breaking down as described below.

[0097] Here, the IGBT of Example 3 will be described in detail. Image 6 It is a cross-sectional view of an important part of an IGBT according to Example 3 of the present invention. Right and Picture 9 The same parts are marked with the same reference numbers. Image 6 IGBT and Figure 4 The difference between the MOSFET is that the IGBT includes p + Collector layer 14, located at p + Collector layer 14 and n - N between drift layers 1 + Buffer layer 15, an...

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PUM

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Abstract

An object of the present invention is to provide a MOS type semiconductor device allowing production at a low cost without lowering a breakdown voltage and avoiding increase of an ON resistance. A MOS type semiconductor device of the invention comprises: a p base region (17) having a bottom part in a configuration with a finite radius of curvature and selectively disposed on a front surface region of a n-drift layer (1); an n type first region (6) selectively disposed on a front surface region of the p base region (17); a gate electrode (8) disposed on a part of the surface of the p base region (17) between a surface of the n type first region (6) and a front surface of the n-drift layer (1) interposing a gate insulation film (10) between the part of the surface of the p base region (17) and the gate electrode (8); and a metal electrode (13) in electrically conductive contact with the front surface of the n type first region (6) and the central part of the surface of the p base region (17); wherein a pn junction surface between the base region and the drift layer has centers of curvature both at the outside and inside of the base region.

Description

[0001] Cross references to related applications [0002] This application is based on Japanese Patent Application No. 2010-173563 filed on August 2, 2010 and claims the priority of this application, and the content of this application is incorporated herein by reference. Technical field [0003] The present invention relates to MOS type semiconductor devices such as MOSFET (MOS Field Effect Transistor), IGBT (Insulated Gate Bipolar Transistor), and a method of manufacturing such MOS type semiconductor device. Background technique [0004] Power MOSFETs and IGBTs are both MOS-type semiconductor devices and are known to the public as voltage-controllable devices. Picture 9 It is a cross-sectional view of an important part of a conventional IGBT. N + Drain layer 2 adjacent n - A p base region 17 is formed on the front layer of the drift layer 1. On the front area of ​​the p base region 17 is selectively formed n + Source region 6 and p + Contact area 22. At n - Surface of drift layer...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/78H01L29/06H01L29/10H01L29/739H01L21/336
CPCH01L29/0626H01L29/0696H01L29/0878H01L29/1095H01L29/41766H01L29/6634H01L29/66712H01L29/66727H01L29/7395H01L29/7802
Inventor 新村康
Owner FUJI ELECTRIC CO LTD