MOS (metal oxide semiconductor) transistor and manufacturing method of MOS transistor gate dielectric layer

Abstract

The invention relates to a manufacturing method of an MOS (metal oxide semiconductor) transistor gate dielectric layer. The manufacturing method comprises the following steps of: providing a semiconductor substrate, wherein a false gate dielectric layer and a dielectric protective layer are formed on the semiconductor substrate, and a gate opening is formed in the dielectric protective layer and leads the false gate dielectric layer to be exposed; forming a sacrificial layer on the dielectric protective layer and in the gate opening, wherein the sacrificial layer covers the gate opening in a shape-maintaining manner; etching the sacrificial layer in an anisotropic manner, and only retaining the sacrificial layer on the vertical side wall of the gate opening; forming a high-K dielectric material on the dielectric protective layer and in the gate opening, wherein the high-K dielectric material covers the gate opening in a shape-maintaining manner; and carrying out annealing treatment on the semiconductor substrate and leading the sacrificial layer on the vertical side wall of the gate opening and the high-K dielectric material to react to form a mixed dielectric layer which has a dielectric constant less than that of the high-K dielectric material. In the manufacturing method, a high-K gate dielectric layer at the bottom part of the metal gate is not damaged and simultaneously the gate parasitic capacitance is reduced.

Description

technical field [0001] The present invention relates to the technical field of semiconductors, and more specifically, the present invention relates to a manufacturing method of a MOS transistor and a gate dielectric layer thereof. Background technique [0002] With the continuous development of integrated circuit manufacturing technology, the feature size of MOS transistors is getting smaller and smaller. In the case of continuous shrinking of the feature size of MOS transistors, in order to reduce the parasitic capacitance of the gate of MOS transistors and improve the device speed, the gate stack structure of high K gate dielectric layer and metal gate (High K Metal Gate, HKMG) was introduced. into the MOS transistor. [0003] In order to avoid the influence of the gate metal material of the metal gate on other structures of the transistor, the gate stack structure of the metal gate and the high-K gate dielectric layer is usually fabricated by a gate replacement (replacem...

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Problems solved by technology

However, the polysilicon or gate metal material also blocks silicon ion implantation into the high-K gate dielectric layer on the vertical sidewall of the gate opening, so that the high-K gate dielectric layer at this position has only a partial area of ​​dielectric constant can be reduced, but the gate parasitic capacitance is still difficult to effectively reduce

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