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Method for effectively reducing the influence of via etch stop layer strain process on pmos

A technology of through-hole etching and stop layer, applied in electrical components, semiconductor/solid-state device manufacturing, circuits, etc., can solve the problem of PMOS device characteristic attenuation and other problems, and achieve the effect of reducing characteristic attenuation

Active Publication Date: 2016-01-27
SHANGHAI HUALI MICROELECTRONICS CORP
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Problems solved by technology

[0005] The invention discloses a method for effectively reducing the influence of the through-hole etch-stop layer strain process on PMOS, which is used to solve the problem of silicon nitride with only tensile stress in the prior art through-hole etch-stop layer technology, making NMOS devices While the performance is improved, the characteristics of the PMOS device will be attenuated to a certain extent

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  • Method for effectively reducing the influence of via etch stop layer strain process on pmos
  • Method for effectively reducing the influence of via etch stop layer strain process on pmos
  • Method for effectively reducing the influence of via etch stop layer strain process on pmos

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Embodiment Construction

[0024] The specific embodiment of the present invention will be further described below in conjunction with accompanying drawing:

[0025] figure 1 It is a schematic diagram after the first transistor and the second transistor are formed on the silicon substrate of the method for effectively reducing the influence of the via etch stop layer strain process on the PMOS in the present invention, please refer to figure 1 , a method for effectively reducing the influence of a through-hole etching stop layer strain process on PMOS, forming a first transistor 101 and a second transistor 201 on a silicon substrate, which includes the following steps:

[0026] figure 2 It is a schematic diagram of the method for effectively reducing the influence of the through-hole etch stop layer strain process on PMOS in the present invention after forming the etch stop layer, please refer to figure 2 , step a: growing an etch barrier layer 301 on the silicon substrate, the etch barrier layer 30...

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Abstract

The invention discloses a method for effectively reducing the influence of a through hole etching stopping layer process to a PMOS (P-channel Metal Oxide Semiconductor), which is used for solving the problem of weakening the character of a PMOS device to a certain extent while improving the performance of an NMOS (N-channel Metal Oxide Semiconductor) device due to existence of silicon nitride only with tensile stress in a through hole etching stopping layer technical process. A silicon nitride thin film with the tensile stress in a PMOS region is subjected to a certain processing through a certain fabrication processing method (concretely comprising UV processing, heavy ion bombarding, such as Sn, Kr and the like), and the inherent crystal structure of the silicon nitride thin film is damaged, so that the intrinsic tensile stress of the silicon nitride thin film is released to achieve the aim of weakening the character of the PMOS device.

Description

technical field [0001] The invention relates to a semiconductor process, in particular to a method for effectively reducing the influence of the through-hole etching stop layer strain process on PMOS. Background technique [0002] In the first-generation CESL process, usually only tensile-stressed silicon nitride is used. Since the stress types required by NMOS and PMOS are opposite, this kind of stress film improves the characteristics of NMOS devices while improving the performance of PMOS devices. The characteristics will be attenuated to a certain extent. [0003] A. Shimizu reported on IEDM in 2002 a method of using Ge implantation to adjust the influence of CESL process to eliminate the deterioration of CESL process for PMOS. [0004] In its deep sub-micron process, the IBM Alliance uses Xe implantation to reduce the impact of CESL process on PMOS. In 2006, Chinese patent 200510074788.1 proposed to protect a method of implanting PMOS region by ion implantation method ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/8238
Inventor 曹永峰
Owner SHANGHAI HUALI MICROELECTRONICS CORP