Dense-pitch small-pad copper-wire bonded single intelligent card (IC) chip packing piece and preparation method thereof

Abstract

The invention relates to a dense-pitch small-pad copper-wire bonded single intelligent card 9IC) chip packing piece, which is characterized in that: a lead framework carrier and framework lead inner pins are arranged inside a plastic-sealed body, the lead framework carrier is fixedly connected with an IC chip, the IC chip is provided with a plurality of welding pads corresponding to the framework lead inner pins one by one, each welding pad iis connected with the corresponding framework lead inner pin through a bonding line, a bold ball is respectively welded on a welding pad or on a spaced welding pad in each welding pad group, each gold ball is connected with a first copper bonding ball in a welding way, a crescent copper welding point is punched on the corresponding inner pin to form a first copper bonding line; and the welding pad which is not connected with the gold ball is connected with a second copper bonding ball in a welding way, a crescent copper welding point is also punched on the corresponding inner pin to form a second copper bonding line, and the gold balls in two rows of welding pad groups are alaternatively arranged. Due to the adoption of the packing piece and the preparation method, the open-circuit potential danger of a plastic-sealed punching line caused by a crater on the welding pad, short circuit of two adjacent welding points and a previous line is easy to damage can be avoided.

Description

technical field

[0001] The invention belongs to the technical field of electronic information automation components manufacturing, and relates to an IC chip package, specifically a single IC chip package with fine-pitch small pad copper wire bonding, and the invention also relates to the preparation of the package method. Background technique

[0002] With the rapid development of the electronic information industry, the chip manufacturing industry has entered the nanometer era, and the process size of chip manufacturing has shrunk from 90nm to 45nm, and then to 30nm and 13nm. The geometric size of the chip is also getting smaller and smaller, from 1.0mm×1.0mm to 0.8mm×0.8mm, 0.5mm×0.5mm, 0.3mm×0.3mm, and the minimum is 0.15mm×0.15mm. Correspondingly, the chip used in chip manufacturing The pad pitch is also gradually reduced from 120μm to 100μm, 70μm, 60μm, 50μm and 45μm. The scribe line is also gradually reduced from 100 μm to 70 μm, 60 μm, 50 μm and 45 μm. The pad si...

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