Dense-pitch small-pad copper-wire bonded single intelligent card (IC) chip packing piece and preparation method thereof

A chip package and small pad technology, which is applied in semiconductor/solid-state device manufacturing, electrical components, electric solid-state devices, etc., can solve the problems of short circuit of adjacent solder joints, damage of adjacent bonding wires, etc., and achieve bonding strength Excellent, save the cost of welding wire, improve the effect of product quality

Active Publication Date: 2012-05-02
TIANSHUI HUATIAN TECH +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] In order to solve the problems of short circuits between adjacent solder joints and damage to adjacent solder wires in the existing fine-pitch small pad IC chip copper wire bonding with a pitch of ≤43 μm and 38 μm×38 μm, the present invention provides an adjacent A copper wire bonded single IC chip package with fine-pitch sma...

Method used

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  • Dense-pitch small-pad copper-wire bonded single intelligent card (IC) chip packing piece and preparation method thereof
  • Dense-pitch small-pad copper-wire bonded single intelligent card (IC) chip packing piece and preparation method thereof
  • Dense-pitch small-pad copper-wire bonded single intelligent card (IC) chip packing piece and preparation method thereof

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Experimental program
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Effect test

Embodiment 1

[0035] The process flow of preparing packages is thinning, scribing, core bonding, pressure welding, plastic sealing, post-curing, rib cutting, electroplating, printing, forming separation and packaging, in which other processes except core core and pressure welding processes are adopted The conventional method of related packaging forms, the process of chipping and bonding operation is as follows:

[0036] 1. Thinning and scribing

[0037]Thinning the wafer to 280μm and dicing by adopting general packaging thinning equipment and process;

[0038] 2. Core loading

[0039] Using the eSOP, eMSOP, eTSSOP, e / TLQFP, QFN, DFN lead frame with the exposed carrier, fix the 1 thinned and diced IC chip 3 on the above lead frame carrier 1 with adhesive 2, the core loading equipment and process Production of conventional products in the same packaging form;

[0040] 3. Baking

[0041] Use N 2 The anti-separation layer baking technology with an air flow rate of 25ml / min bakes the lead ...

Embodiment 2

[0052] 1. Thinning and scribing

[0053] Thinning the wafer to 300μm and dicing by adopting general packaging thinning equipment and process;

[0054] 2. Core loading

[0055] Using eSOP, eMSOP, eTSSOP, e / TLQFP, QFN, DFN lead frame with exposed carrier, fix 1 IC chip 3 that has been thinned and diced on the above lead frame carrier 1 with conductive glue, and the chipping equipment and process are related to the same Production of conventional products in package form;

[0056] 3. Baking

[0057] Use N 2 The anti-separation layer baking technology with an air flow rate of 30ml / min bakes the lead frame carrier for 3 hours at a baking temperature of 150°C;

[0058] 4. Pressure welding

[0059] (1) Two rows of pad groups are arranged in parallel on the upper surface of the IC chip 3 installed in step 1, and the two rows of pad groups are respectively composed of the same or different numbers of pads 4, and each pad in the two rows 4 are not in contact with each other, the p...

Embodiment 3

[0070] 1. Thinning and scribing

[0071] Use relevant packaging forms to thin general-purpose equipment and processes, and wafers are thinned by 250 μm and diced;

[0072] 2. Core loading

[0073] The upper core adopts SOP, SSOP, MSOP, TSSOP, QFPL, QFP, QFN, DFN lead frame with no exposed carrier, and the IC chip 3 that has been thinned to 250 μm and diced is fixed on the above lead frame carrier 1 with insulating glue , the chip-on equipment and process are the same as those of conventional products in related packaging forms;

[0074] 3. Pressure welding

[0075] (1) On the upper surface of the IC chip 3 installed in step 1, two rows of pad groups are arranged in parallel, and the two rows of pad groups are respectively composed of the same number of pads 4, and the gap between each pad 4 in the two rows of pad groups is Not in contact with each other, the pads 4 in one row of pad groups correspond to the pads 4 in the other row of pad groups, such as figure 1 As shown, ...

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Abstract

The invention relates to a dense-pitch small-pad copper-wire bonded single intelligent card 9IC) chip packing piece, which is characterized in that: a lead framework carrier and framework lead inner pins are arranged inside a plastic-sealed body, the lead framework carrier is fixedly connected with an IC chip, the IC chip is provided with a plurality of welding pads corresponding to the framework lead inner pins one by one, each welding pad iis connected with the corresponding framework lead inner pin through a bonding line, a bold ball is respectively welded on a welding pad or on a spaced welding pad in each welding pad group, each gold ball is connected with a first copper bonding ball in a welding way, a crescent copper welding point is punched on the corresponding inner pin to form a first copper bonding line; and the welding pad which is not connected with the gold ball is connected with a second copper bonding ball in a welding way, a crescent copper welding point is also punched on the corresponding inner pin to form a second copper bonding line, and the gold balls in two rows of welding pad groups are alaternatively arranged. Due to the adoption of the packing piece and the preparation method, the open-circuit potential danger of a plastic-sealed punching line caused by a crater on the welding pad, short circuit of two adjacent welding points and a previous line is easy to damage can be avoided.

Description

technical field [0001] The invention belongs to the technical field of electronic information automation components manufacturing, and relates to an IC chip package, specifically a single IC chip package with fine-pitch small pad copper wire bonding, and the invention also relates to the preparation of the package method. Background technique [0002] With the rapid development of the electronic information industry, the chip manufacturing industry has entered the nanometer era, and the process size of chip manufacturing has shrunk from 90nm to 45nm, and then to 30nm and 13nm. The geometric size of the chip is also getting smaller and smaller, from 1.0mm×1.0mm to 0.8mm×0.8mm, 0.5mm×0.5mm, 0.3mm×0.3mm, and the minimum is 0.15mm×0.15mm. Correspondingly, the chip used in chip manufacturing The pad pitch is also gradually reduced from 120μm to 100μm, 70μm, 60μm, 50μm and 45μm. The scribe line is also gradually reduced from 100 μm to 70 μm, 60 μm, 50 μm and 45 μm. The pad si...

Claims

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Application Information

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IPC IPC(8): H01L23/498H01L23/49H01L21/60H01L21/50
CPCH01L2224/45015H01L2924/01029H01L2924/01082H01L2224/4848H01L2924/01079H01L2224/48091H01L2224/48465H01L2224/49175H01L2224/48247H01L24/06H01L2224/45147H01L2224/04042H01L2224/05554H01L2224/48482H01L2224/48499H01L2224/73265H01L2924/00011H01L2924/14H01L2924/181H01L2924/00014H01L2924/20753H01L2924/00H01L2924/00012H01L2924/01005H01L2924/01004H01L2924/01033H01L2924/20751
Inventor 慕蔚李习周郭小伟
Owner TIANSHUI HUATIAN TECH
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