Single Damascus method used for reducing square resistance of copper interconnection

A technology of sheet resistance and copper interconnection, which is applied in the manufacture of circuits, electrical components, semiconductor/solid-state devices, etc., can solve the shape and size of unfavorable etching process etching, reduce interconnect reliability, and increase sheet resistance, etc. problem, to achieve the effect of reducing chip interconnection sheet resistance, interconnection sheet resistance, and signal delay

Active Publication Date: 2012-05-09
SHANGHAI HUALI MICROELECTRONICS CORP
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Problems solved by technology

Because the thickness is too thick, it means that the depth of the trench structure is very large, which will not be conducive to the etching process to control the shape and size of the etching, and t

Method used

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  • Single Damascus method used for reducing square resistance of copper interconnection
  • Single Damascus method used for reducing square resistance of copper interconnection
  • Single Damascus method used for reducing square resistance of copper interconnection

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Embodiment Construction

[0034] The invention provides a single damascene method for reducing the sheet resistance of copper interconnects. The single damascene process is used to add the lower half of the copper interconnection that needs to reduce the sheet resistance in the through-hole layer. This layer requires two photolithographic etching processes. Then, metal filling and chemical mechanical polishing are performed to obtain the first part of the copper interconnection with reduced sheet resistance. Then, a single damascene process is used to construct a metal trench, and the thickness of the trench of all metal wires in this layer is the same. Due to the alignment of the upper and lower layers, there are also copper interconnects pre-set in the first layer under some metal wires. Therefore, compared with ordinary interconnects, this part of the copper interconnects has a thicker metal thickness. , Or there are two interconnections in parallel, so a lower sheet resistance is obtained.

[0035] ...

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Abstract

The invention provides a single Damascus method used for reducing the square resistance of a copper interconnection. In the invention, a single Damascus process is adopted, a through hole layer is additionally provided with an extra metal interconnection used for reducing the square resistance of the copper interconnection, and the through hole layer and the copper metal wire of the next single Damascus layer are combined, thus finally obtaining a copper interconnection line with lower square resistance. According to the method provided by the invention, the depth of a groove of the copper interconnection line can be selectivity changed, thereby reducing the square resistance of the copper interconnection line of a specified area meeting conditions, and realizing the purpose of selectively reducing the square resistance of the chip interconnection; and on the premise of not changing the whole copper interconnection depth, not increasing the process difficulty and not reducing the process window, the square resistance of the interconnection is farthest reduced, thereby reducing the signal delay of a chip, reducing the loss and improving the overall performance of the chip.

Description

Technical field [0001] The invention relates to the field of semiconductor manufacturing, and in particular to a single damascene method for reducing copper interconnection square resistance. Background technique [0002] In the semiconductor integrated circuit industry, high-performance integrated circuit chips require high-performance back-end electrical interconnections. Because of the low resistivity of metallic copper, it has been more and more widely used in advanced integrated circuit chips. From aluminum wire to copper wire, changes in materials have brought about a huge decrease in resistivity. With the advancement of integrated circuit technology, the complexity of the chip has increased, and the complexity and length of the back-end interconnection have become larger and larger, which means that the resistance of the back-end interconnection line in the chip has become one of the bottlenecks in performance. Effectively reducing resistance has become an important rese...

Claims

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Application Information

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IPC IPC(8): H01L21/768
Inventor 姬峰张亮胡友存李磊陈玉文
Owner SHANGHAI HUALI MICROELECTRONICS CORP
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