Method for forming semiconductor structure

Abstract

The invention provides a method for forming a semiconductor structure, comprising the following steps of: providing a substrate, wherein the substrate is provided with a grid structure, a source region and a drain region positioned in the substrate at the two sides of the grid structure; forming metal layers on the surfaces of the source region and the drain region; and carrying out annealing process on the source region and the drain region forming the metal layers on the surfaces, and forming metal silicide in the source region and the drain region, wherein annealing gas at least comprises one or combination of hydrogen and deuterium. According to the method, by adding one or combination of the hydrogen and the deuterium into the annealing gas, silicon dangling bonds in the substrate are bonded with one or combination of the hydrogen and the deuterium, the silicon dangling bonds in the substrate are reduced, the interface defects nearby the substrate are reduced, and silicon-hydrogen bonds and silicon-deuterium bonds are stronger respectively, the cracking probability of the silicon-hydrogen bonds and the silicon-deuterium bonds is reduced under the external stress of the process environment, the interface defects nearby the substrate are further reduced, and the hot electron effect is restrained.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for forming a semiconductor structure. Background technique [0002] The main device in an integrated circuit, especially a VLSI, is a Metal Oxide Semiconductor (MOS for short). Since the invention of the integrated circuit, its performance and function have advanced by leaps and bounds, and the geometric size of the MOS device has been continuously reduced, and its feature size has entered the nanometer scale. [0003] In the process of scaling down the MOS device, the drain voltage does not decrease accordingly, which leads to the increase of the electric field in the channel region between the source and the drain. These electrons are called hot electrons, which are injected into the gate dielectric layer, thereby causing hot electron effect. This effect belongs to the small size effect of the device, which will cause gate electrode current and semiconduct...

AI Technical Summary

Problems solved by technology

However, these improvements do not involve reducing the probability of carriers being trapped in the oxide layer, that is, how to effectively reduce the interface states in the gate oxide layer (mainly the interface traps that capture carriers) to improve the hot electron effect

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