Interface trap testing method for shallow trench isolation (STI) type laterally diffused metal oxide semiconductor (LDMOS) device
An interface trap and test method technology, applied in the direction of single semiconductor device testing, etc., can solve the problems of gate oxide loss, damage, and the inability of charge pump technology to fully use STI type LDMOS devices, so as to save test costs and reduce costs. deterministic effect
Active Publication Date: 2013-12-11
PEKING UNIV
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Problems solved by technology
For STI type LDMOS devices, if the conventional charge pump technology is used, only the interface trap density in the channel region can be obtained; since the thickness of the oxide layer in the STI region is much larger than the thickness of the gate oxide layer in the channel region, in order to obtain the interface trap density in the STI region Therefore, it is necessary to increase the value of the pulse voltage applied to the gate, so that the gate voltage will be greater than the power supply voltage during normal operation, which will cause loss and damage to the gate oxide layer during the measurement process.
Therefore, conventional charge pump technology cannot be fully utilized in STI type LDMOS devices
Method used
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[0027] The specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and embodiments. The following examples are intended to illustrate the present invention, but not to limit the scope of the present invention.
[0028] The test structure adopted in the present invention is an STI type LDMOS device, and no additional test structure needs to be designed. Taking NLDMOS device as an example, the structure diagram is as follows figure 1 Shown is a four-terminal device including source, gate, drain, and substrate, where the black line represents the interface between the gate oxide and the STI region and the silicon, and the channel length Lch should be greater than or equal to that allowed by the process node. The shortest channel length, while the channel width is a fixed value much larger than the minimum width.
[0029] The structure test circuit of the method of the present invention is as follows: ...
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The invention discloses an interface trap testing method for a shallow trench isolation (STI) type laterally diffused metal oxide semiconductor (LDMOS) device and relates to the technical field of reliability of high-voltage semiconductor devices. The method comprises the following steps of: applying the same positive bias voltage between a source of the STI type LDMOS device and a substrate and between a drain of the STI type LDMOS device and the substrate, and simultaneously applying grid scanning voltage; and measuring the current of the substrate, and determining that the interface trap is positioned in an STI region or a trench region of the LDMOS device through a peak position of the current of the substrate. The STI type LDMOS device is directly used as a testing structure, and the testing cost is saved; and moreover, the position of the interface trap in the STI region or the trench region is convenient to acquire in a test, and the STI type LDMOS device is not damaged.
Description
technical field [0001] The invention relates to the technical field of reliability of high-voltage semiconductor devices, in particular to an interface trap testing method of an STI type LDMOS device. Background technique [0002] Laterally Diffused Metal Oxide Semiconductor (LDMOS, Laterally Diffused Metal Oxide Semiconductor) is a high-voltage semiconductor device widely used in RF base stations, Plasma Display Panel (PDP) display drivers, power management, and automotive electronics. . Compared with the traditional Insulated Gate Bipolar Transistor (IGBT), it has higher response speed and lower leakage current, and has greater advantages in process integration as a planar device. Adding a shallow trench isolation (STI) region to the drift region of traditional LDMOS devices can effectively increase the breakdown voltage of high-voltage devices and improve the on-state resistance of devices. STI-type LDMOS devices have been widely used . Because in most applications, th...
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IPC IPC(8): G01R31/26
Inventor 何燕冬张钢刚刘晓彦张兴
Owner PEKING UNIV