Voltage regulator and method for generating pulse width modulation signal thereof

Abstract

The invention relates to a voltage regulator and a method for generating pulse width modulation signal thereof, and the method includes steps as follows: providing an output sensing signal including an output voltage error signal; providing a first ramp signal, and determining a start point of an on period of a pulse width modulation signal according to a first intersection point of the first ramp signal and the output sensing signal; and providing a second ramp signal, and determining an end point of the on period of the pulse width modulation signal according to a second intersection point of the second ramp signal and the output sensing signal. The first ramp signal is reset to a reference voltage at the first intersection point and maintained at the reference voltage, and begins to climb downwards at the end point of the on period of the pulse width modulation signal; and the second ramp signal begins to climb upwards at the start point of the on period of the pulse width modulation signal, and is reset to a preset electric potential at the second intersection point. According to the invention, the on period of the pulse width regulation signal can give a quick transient response to the change of the output sensing signal relevant to the load change, thereby greatly improving the performance of the voltage regulator.

Description

Technical field [0001] The present invention relates to power regulators or converters, and more particularly to voltage regulators and methods for generating pulse width modulation signals. Background technique [0002] The load current of today's central processing unit (CPU) is highly dynamic and changes from low to high and from high to low very quickly. The current transient of the CPU may occur within 1 microsecond, which may be less than the typical switching period of the existing voltage regulator. Therefore, the industry hopes to provide a DC-to-DC voltage regulator with a control loop (for example, a voltage mode or a current mode control loop), which can provide an almost real-time transient response to load changes to regulate an accurate output voltage. [0003] In the pulse width modulation design of the existing voltage regulator, a single ramp signal or a dual ramp signal is induced by a fixed frequency (constant frequency) synchronous clock signal to be used as a...

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Problems solved by technology

[0004] However, from figure 1 It can be found that since the ramp signal RAMP is limited by the synchronous pulse signal CLK and is fixed, it is difficult for the existing pulse width modulation design to make the on-period of the pulse width modulation signal PWM respond to the instant of the output voltage error signal COMP caused by the load change. change (eg figure 1 Protruding part of the COMP) to respond in real time

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