Method for improving erasing speed of SONOS memory
A technology for erasing and writing speed and memory, which is applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., and can solve the problem of low efficiency of hot electron injection programming
Inactive Publication Date: 2012-07-04
SHANGHAI HUALI MICROELECTRONICS CORP
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Problems solved by technology
When some electrons get enough high energy, hot electron injection occurs, but since only a small part of the channel is effective for programming, hot electron injection programming is not efficient
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[0032] In order to further illustrate the technical means and effects that the present invention adopts to achieve the intended invention purpose, a method for improving the erasing and writing speed of SONOS memory according to the present invention is described in detail below in conjunction with the accompanying drawings and preferred embodiments.
[0033] Different embodiments of the present invention will be described in detail below to implement different technical features of the present invention. It should be understood that the units and configurations of the specific embodiments described below are used to simplify the present invention, which are only examples and not limiting scope of the invention.
[0034] figure 1 It is a typical structure of traditional SONOS memory. refer to figure 1 , drain and source regions 2 and 3 are spaced apart at the surface of the substrate 1 . A gate oxide layer 4 is arranged on the substrate 1 between the drain and source region...
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The invention provides a method for improving the erasing speed of an SONOS (Silicon Oxide Nitride Oxide Silicon) memory by adopting channel stress engineering. The method comprises the following steps: a semiconductor underlay is provided; a P-well region and an N-well region are formed on the semiconductor underlay; an oxide layer is formed on the semiconductor underlay provided with the P-well region and the N-well region; shallow trench isolation (STI) is formed in the semiconductor underlay and the oxide layer; Ge ions are injected into an NMOS (N-channel Metal Oxide Semiconductor) region, and then a Si layer is covered, so as to form a SiGe low electric filed channel; a grid oxide layer and a polycrystalline silicon layer are formed on the well regions and the STI, and form a control grid pattern; and a source region and a drain region are formed on two opposite sides of the control grid pattern. With the view to improve the channel carrier mobility, the method provided by the invention improves the electron mobility by adopting the channel stress engineering, ameliorates the SONOS programming efficiency and the speed of a hot electron injection mechanism, and has a very high practicality.
Description
technical field [0001] The invention relates to a silicon-silicon-oxide-silicon-nitride silicon-oxide-silicon (SONOS) memory, in particular to a method for improving the erasing and writing speed of the SONOS memory. Background technique [0002] Memory can be roughly divided into two categories: volatile memory and non-volatile memory. Volatile memory loses the information stored in it immediately when the system is connected, and it requires a continuous power supply to maintain the data. Most random access memory (RAM) is volatile memory. Non-volatile memory can continue to retain data information when the system is disconnected or there is no power supply. Non-volatile memory can be further divided into two types, charge trap type memory and floating gate type memory. In floating-gate memory, charges are stored in the floating gate, where they remain in the absence of a power supply. The amount of charge stored in the floating gate can affect the threshold voltage of...
Claims
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Inventor 刘格致黄晓橹
Owner SHANGHAI HUALI MICROELECTRONICS CORP