Single electron transistor (SET)/metal oxide semiconductor (MOS) mixed structure multiplier unit based on threshold logic

Abstract

The invention relates to the technical field of integrated circuits, in particular to a single electron transistor (SET) / metal oxide semiconductor (MOS) mixed structure multiplier unit based on threshold logic, which comprises a first signal source, a second signal source, a third signal source, a fourth signal source, a fourth input threshold logic gate, a fifth input threshold logic gate and an inverter. The SET / MOS mixed structure multiplier unit consumes 3 p-channel metal oxide semiconductor (PMOS) pipes, 3 n-channel metal oxide semiconductor (NMOS) pipes and 2 SETs. Simulation results of simulation program with IC emphasis (HSPICE) show that a circuit can effectively achieve logical functions of the multiplier unit, and the average power consumption of the whole circuit is only 12nW. Compared with a complementary metal oxide semiconductor (CMOS) multiplier unit based on Boolean logic, the SET / MOS mixed structure multiplier unit greatly reduces the number of pipes, remarkably reduces power consumption, further simplifies a circuit structure, is favorable for saving area of chips, and improves integration level of the circuit.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to a SET / MOS mixed structure multiplier unit composed of nano devices and based on threshold logic. Background technique [0002] The multiplier is a common combinational logic circuit, which has important applications in microprocessors, digital signal processors and image engines. The traditional CMOS multiplier is composed of multi-stage full adder and AND gate, and its schematic diagram is as follows figure 1 shown. The multiplier consumes more CMOS transistors. With the continuous reduction of CMOS feature size, CMOS technology is facing great challenges, and many problems have appeared in the electrical characteristics and reliability of devices, such as short channel effects, strong field effects, and drain-induced barrier drop effects. At this time, the multiplier based on CMOS transistors has been greatly restricted in terms of operation speed, integration, r...

AI Technical Summary

Problems solved by technology

The multiplier consumes more CMOS transistors

With the continuous reduction of CMOS feature size, CMOS technology is facing great challenges, and many problems have appeared in the electrical characteristics and reliability of devices, such as short channel effects, strong field effects, and drain-induced barrier drop effects, etc.

At this time, the multiplier based on CMOS transistors has been greatly restricted in terms of operation speed, integration, reliability, and power consumption with the increase in the number of operations and the increase in the complexity of the circuit, and it has been unable to meet the new requirements. performance requirements

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