SDLC (System Development Life Cycle) protocol bus communication testing device based on FPGA (Field-Programmable Gate Array)

A test device, bus communication technology, applied in the bus network, data exchange through path configuration, digital transmission system, etc., can solve the problems of unfavorable system integration application, inconvenient installation and operation, complicated operation, etc., to achieve small size and meet the test requirements , the effect of strong versatility

Active Publication Date: 2014-06-04
SHANGHAI WORKPOWER TELECOM TECH
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] At present, a number of error detectors have been developed for bit error testing. The signal delay can be monitored by an oscilloscope, but due to its high cost, large size, and complicated operation, it is not conducive to system integration applications, especially for functional testing, sophisticated, In the test process of temperature cycle, high and low temperature, random vibration, noise and transportation, a large number of test equipment must be transferred with the product, which is very inconvenient to install and operate

Method used

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  • SDLC (System Development Life Cycle) protocol bus communication testing device based on FPGA (Field-Programmable Gate Array)
  • SDLC (System Development Life Cycle) protocol bus communication testing device based on FPGA (Field-Programmable Gate Array)
  • SDLC (System Development Life Cycle) protocol bus communication testing device based on FPGA (Field-Programmable Gate Array)

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Embodiment 1

[0026] See attached figure 2 , connector 4 of the present invention is connected to the tested module 8 of the product, and FPGA test module 1 is used for the test of signal error rate and delay time; Memory 7 provides loading program for FPGA test module 1; Crystal oscillator 6, for FPGA The test module 1 provides a clock source; the differential driver 2 is used to convert the SDLC signal output by the FPGA test module 1 into a differential signal output; the differential receiver 3 is used to convert the input differential signal into a logic signal and send it to the FPGA test module 1 for processing; the computer 5 is used to send test instructions and data to the FPGA test module 1, and receive data from the FPGA test module 1 for data processing.

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Abstract

The invention discloses an SDLC (System Development Life Cycle) protocol bus communication testing device based on FPGA (Field-Programmable Gate Array). The testing device is characterized by being composed of an FPGA test module, a differential driver, a differential receiver, a connector, a computer, a crystal oscillator and a memory, wherein the computer inputs test data to the FPGA test module to form an SDLC sequence, the SDLC sequence is input to the differential driver, the differential driver converts the SDLC sequence into differential signals, the differential signals are input to the connector, the connector inputs test signals of self-tested and tested products to the differential receiver, the differential receiver converts the test signals into logic signals, the logic signals are input to the FPGA test module for performing SDLC protocol decoding, and the computer calculates the error rate and delay time of the tested product. As compared with the prior art, the testing device has the advantages of high testing efficiency, convenience for operation and convenience for system integration, and can automatically change the design content as required so as to meet the testing of special occasions.

Description

technical field [0001] The invention relates to the technical field of communication detection, in particular to an FPGA-based SDLC protocol bus communication testing device. Background technique [0002] At present, in multi-point communication systems, such as weapon systems, industrial distribution systems and commercial POS cash registers, serial communication is generally used in networking. RS-485 is a serial interface standard with a balanced transmission mode. Its characteristics It has strong anti-interference ability, high transmission rate and long transmission distance. When using twisted pair, it allows a maximum transmission rate of 10Mbit / s, and its transmission distance is 15m. RS-485 allows up to 32 transmitter / receiver pairs to be connected on a balanced cable, which has been widely used in many aspects. [0003] A protocol often used in serial communication is the synchronous data link control protocol SDLC. The characteristic of this protocol is that a f...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04L12/26H04L12/40
Inventor 郝斌魁孔令涛
Owner SHANGHAI WORKPOWER TELECOM TECH
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