A method for forming double stress layer silicon nitride film

Abstract

The invention provides a method for forming a silicon nitride film with double stress layers, comprising the following steps that: a substrate with N / P MOS (Metal-Oxide-Semiconductor) transistors is provided; a silicon oxide buffer layer is deposited on the structure; a first silicon nitride stress layer with high compressive stress is deposited on the structure; the PMOS zone is subjected to photo-etching and etching, and the first silicon nitride stress layer and the silicon oxide buffer layer in the P MOS zone are removed; a second silicon nitride stress layer with high tensile stress is deposited on the structure; and the N MOS zone is subjected to photo-etching and etching, and the second silicon nitride stress layer in the N MOS zone is removed. According to the double stress layers prepared by the method, the technique is optimized, the cost is reduced, and meanwhile, the influence of the silicon oxide buffer layer on a grid electrode in the N MOS zone does not exist, so that the electromobility of the N / P MOS can be improved due to the double stress layers prepared by the method, and further, the performance of a device is improved.

Description

technical field [0001] The invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to a method for forming a double stress layer silicon nitride film. Background technique [0002] As the characteristic line width of integrated circuits shrinks below 90nm, people gradually introduce high-stress silicon nitride technology to improve the electrical mobility of carriers. By depositing high-tension and high-pressure-stress silicon nitride on the N / PMOS as a contact etch stop layer (Contact Etch Stop Layer, CESL). Especially below the 65nm process, in order to improve the electrical mobility of N / PMOS at the same time, it is sometimes necessary to deposit high-tension and high-voltage stress silicon nitride on different MOS at the same time, and if there is a compressive stress layer film on the NMOS or on the PMOS When there is a tensile stress film, it will have an adverse effect on the electrical mobility of N / PMOS. [0003] Theref...

AI Technical Summary

Problems solved by technology

Although the film thickness of these two silicon dioxide buffer layers is relatively thin, and the stress is relatively small, but because the two films are closest to the gate, it also has a certain impact on the electrical mobility of N / PMOS.

Images