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Semiconductor device

A semiconductor and device technology, which is applied in the field of semiconductor devices, can solve the problems of redundant square layout, reduced layout density of measured transistors, difficulty in further improving wiring or the layout density of measured transistors, etc., and achieve the effect of increasing layout density

Inactive Publication Date: 2012-08-08
SONY CORP
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  • Abstract
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  • Application Information

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Problems solved by technology

[0006] However, in Patent Document 1, one transistor-to-be-measured is arranged in a square area surrounded by two wirings in the row direction and two wirings in the column direction, so it is difficult to further improve the performance of the wiring or the transistor-to-be-measured. layout density
Furthermore, in Patent Document 2, the square layout of the wiring surrounding the measured transistor is redundant, causing a problem that the arrangement density of the measured transistor is reduced

Method used

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  • Semiconductor device
  • Semiconductor device
  • Semiconductor device

Examples

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no. 1 example

[0043] figure 1 A schematic position on a wafer of a TEG as a semiconductor device according to the first embodiment of the present invention is shown. The product package 1 is arranged on a wafer (not shown in the figure) as a formation area of ​​a semiconductor integrated circuit. although figure 1 Only one product component 1 is shown in , but a plurality of product components 1 may also be provided. Around the product components 1 are provided frame-shaped or grid-shaped scribe lines 2 for separating each product component 1 by dicing the wafer. Inside the scribing line 2 is provided a TEG assembly 3 . The TEG package 3 is an area provided with evaluation circuits for evaluating characteristics of devices of the semiconductor integrated circuits in the product package 1 . The TEG assembly 3 is arranged inside the scribe line 2 along the longitudinal side (e.g., long side) of the product assembly 1 in the vertical direction (longitudinal direction), and arranged along t...

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Abstract

The present disclosure relates to a semiconductor device suitable for being used for an evaluation circuit of a semiconductor integrated circuit. The semiconductor device includes: plural devices to be measured; and a combined array wiring including plural unit array wirings each having a column wiring and a row wiring provided in different layers as well as each connected to any one of the plural devices to be measured, in which the plural unit array wirings are provided in layers different from each other. Therefore, it is possible to increase arrangement density of the devices to be measured by arranging plural unit array wirings so as to partially overlap each other.

Description

[0001] Cross References to Related Applications [0002] The present invention contains subject matter related to the disclosure of Japanese Priority Patent Application JP 2011-024568 filed in the Japan Patent Office on Feb. 8, 2011, the entire content of which is hereby incorporated by reference. technical field [0003] The present invention relates to a semiconductor device suitable for use in an evaluation circuit of a semiconductor integrated circuit. Background technique [0004] When manufacturing semiconductor integrated circuits, a test element group (TEG) is provided in a wafer for evaluating characteristics of devices included in the product. For example, JP-A-2008-140965 (Patent Document 1) discloses a technique in which a plurality of transistors to be measured are arranged in a matrix state in a TEG, and active terminals are commonly arranged. [0005] It is known that the size and characteristics of semiconductor devices such as transistors and resistors vary...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/544G01R31/28
CPCH01L21/822H01L21/82H01L23/544H01L23/522G01R31/28H01L27/04H01L22/34H01L2924/0002H01L2924/00
Inventor 黛哲
Owner SONY CORP
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