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Signal operation instruction (SOI) transverse super junction power metal oxide semiconductor field effect transistor (MOSFET) device

A technology of lateral superjunction power and devices, which is applied to semiconductor devices, electrical components, circuits, etc., and can solve problems such as low withstand voltage and serious self-heating effect

Inactive Publication Date: 2014-08-20
ZHONGBEI UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] In order to solve the problems of low withstand voltage and serious self-heating effect of the existing SOI lateral super-junction power MOSFET device, the present invention provides a SOI lateral super-junction power MOSFET device

Method used

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  • Signal operation instruction (SOI) transverse super junction power metal oxide semiconductor field effect transistor (MOSFET) device
  • Signal operation instruction (SOI) transverse super junction power metal oxide semiconductor field effect transistor (MOSFET) device
  • Signal operation instruction (SOI) transverse super junction power metal oxide semiconductor field effect transistor (MOSFET) device

Examples

Experimental program
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Effect test

Embodiment 1

[0015] The SOI lateral superjunction power MOSFET device includes a p-type substrate 1, an insulating buried layer 2 disposed on the upper end surface of the p-type substrate 1, and a superjunction n-region 9 and a superjunction p-region 10 alternately distributed laterally. Junction structure; one side of the super junction structure is provided with a p-type body region 3; the upper end surface of the p-type body region 3 is respectively provided with an n-type source region 4, a p-type body contact region 5, and a gate oxide layer 7; n-type The upper end surface of the source region 4 and the upper end surface of the p-type body contact region 5 are jointly provided with a source electrode 6; the upper end surface of the gate oxide layer 7 is provided with a polysilicon gate 8; the other end surface of the super junction structure is provided with an n-type drain region 12; the upper end surface of the n-type drain region 12 is provided with a drain electrode 11; the upper e...

Embodiment 2

[0021] The SOI lateral superjunction power MOSFET device includes a p-type substrate 1, an insulating buried layer 2 disposed on the upper end surface of the p-type substrate 1, and a superjunction n-region 9 and a superjunction p-region 10 alternately distributed laterally. Junction structure; one side of the super junction structure is provided with a p-type body region 3; the upper end surface of the p-type body region 3 is respectively provided with an n-type source region 4, a p-type body contact region 5, and a gate oxide layer 7; n-type The upper end surface of the source region 4 and the upper end surface of the p-type body contact region 5 are jointly provided with a source electrode 6; the upper end surface of the gate oxide layer 7 is provided with a polysilicon gate 8; the other end surface of the super junction structure is provided with an n-type drain region 12; the upper end surface of the n-type drain region 12 is provided with a drain electrode 11; the upper e...

Embodiment 3

[0027] The SOI lateral superjunction power MOSFET device includes a p-type substrate 1, an insulating buried layer 2 disposed on the upper end surface of the p-type substrate 1, and a superjunction n-region 9 and a superjunction p-region 10 alternately distributed laterally. Junction structure; one side of the super junction structure is provided with a p-type body region 3; the upper end surface of the p-type body region 3 is respectively provided with an n-type source region 4, a p-type body contact region 5, and a gate oxide layer 7; n-type The upper end surface of the source region 4 and the upper end surface of the p-type body contact region 5 are jointly provided with a source electrode 6; the upper end surface of the gate oxide layer 7 is provided with a polysilicon gate 8; the other end surface of the super junction structure is provided with an n-type drain region 12; the upper end surface of the n-type drain region 12 is provided with a drain electrode 11; the upper e...

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Abstract

The invention relates to a power semiconductor device, in particular to a signal operation instruction (SOI) transverse super junction power metal oxide semiconductor field effect transistor (MOSFET) device, which solves the problems that the withstand voltage of the exiting SOI transverse super junction power MOSFET device is low, and the natural effect is serious. The SOI transverse super junction power MOSFET device comprises a p type substrate, an insulation burying layer and a super junction structure, wherein the insulation burying layer is arranged at the upper end surface of the p type substrate, the super junction structure consists of a super junction n region and a super junction p region in transverse alternate distribution, the upper end surface of the insulation burying layer is provided with an n type burying layer, the upper end surface of the n type burying layer is provided with a p type epitaxial layer, and a p type body region and the super junction structure are respectively arranged on the upper end surface of the p type epitaxial layer. The SOI transverse super junction power MOSFET device is suitable for being used as a key device in a power integrated circuit (PIC) and can be applied to the fields of motor control, flat plate display driving, computer peripheral equipment control and the like.

Description

technical field [0001] The invention relates to a power semiconductor device, in particular to an SOI lateral superjunction power MOSFET device. Background technique [0002] Power semiconductor devices are playing an increasingly important role in the national economy and social life, and are widely used in consumer electronics, industrial control and defense equipment. Among them, the lateral power MOSFET device represented by LDMOS (Lateral Double-diffused MOSFET) is a key device in a power integrated circuit (PIC, Power Integrated Circuit), and has been used in motor control, flat panel display drive, computer peripheral control and other fields. widely used. With the development of power electronics technology, higher requirements are put forward for the performance of high withstand voltage, high speed and low power consumption of power semiconductor devices. In this regard, people apply super junction structure and SOI (Silicon-On-Insulator, silicon on insulating su...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/78H01L29/06
CPCH01L29/0634H01L29/0649H01L29/1083H01L29/7835
Inventor 王文廉王玉
Owner ZHONGBEI UNIV