Content addressable memory
A technology for addressing memory and content, applied in the field of content addressable memory, which can solve the problems of increased manufacturing cost, reduced data storage area, and reduced memory space
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no. 1 example
[0037] Embodiments will be described below with reference to the drawings. figure 1 A spin MOS field effect transistor (spin MOSFET) is shown. The spin MOSFET 1 has a source / drain (S / D) electrode 3 . The S / D poles 3 are made of a magnetic substance (spin polarized material), and are separated from each other on the semiconductor substrate 2 . While one of the S / D poles 3 has a magnetic layer whose magnetization direction is fixed, the other of the S / D poles 3 has a magnetic layer whose magnetization direction can be changed. Diffusion layers 4 are formed under the S / D electrodes 3, respectively. Between the diffusion layers 4 , a gate insulating film 5 is formed on the semiconductor substrate 2 , and a gate electrode 6 is formed on the gate insulating film 5 .
[0038]In spin MOSFET 1, when a gate voltage is applied to gate 6, a channel is formed in semiconductor substrate 2, and electrons are transported through the channel while maintaining spin polarization. Regarding t...
no. 2 example
[0092] A second embodiment will be described below. The CAM according to the present embodiment is formed of an n-type spin MOSFET or a p-type spin MOSFET. Figure 26 The configuration of a CAM cell that stores 1-bit information in the CAM according to the second embodiment is shown. The CAM cell 200 according to the second embodiment includes two n-type spin MOSFETs and two search lines SL and S'L. A spin MOSFET 41 is connected to SL. Another spin MOSFET 42 is connected to S'L. S'L inputs the inverted value of SL to the spin MOSFET 42. Complementary input values of the pair of wires SL and S'L are realized by a CMOS inverter disposed between them. Although S and D of each spin MOSFET are connected in series, a terminal for measuring the voltage of the substrate for defining the gate voltage can be provided.
[0093]In the second embodiment, as in the first embodiment, CAM cells 200 corresponding to one word are connected in series. Since the inverted value of SL is gi...
no. 3 example
[0096] A third embodiment will be described below. This embodiment shows CAM in the case where one word is larger than 4 bits. As the number of bits per word increases, the voltage of the read signal decreases. Figure 27 and Figure 28 The following output currents and MC ratios are shown under the condition that spin MOSFET pairs corresponding to 8 bits are connected in series: the case where current flows only in parallel magnetized spin MOSFETs (such as Figure 27 and Figure 28 The output current and MC ratio for the case where the search data and the stored data match each other represented by "match" in ; and the case where the current also flows in a spin MOSFET with antiparallel magnetization (such as Figure 27 and Figure 28 The output current and the MC ratio in the case where the search data and the stored data are different from each other by one bit represented by "mismatch" in . Figure 29 and Figure 30 Shown are the following output currents and MC rati...
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