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A method and device for adjusting FPGA bus delay

A bus and delay unit technology, applied in the field of field programmable gate array prototype verification system construction, can solve problems such as low efficiency, unfavorable development speed, and time-consuming, so as to improve effectiveness, improve construction efficiency, and improve adjustment efficiency Effect

Active Publication Date: 2016-08-31
SPREADTRUM COMM (SHANGHAI) CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0013] FPGA bus pins usually have hundreds of pins. It takes a lot of time to manually debug the input and output delays of each pin through an oscilloscope or a logic analyzer. The efficiency is low, which is not conducive to improving the speed of research and development.

Method used

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  • A method and device for adjusting FPGA bus delay
  • A method and device for adjusting FPGA bus delay
  • A method and device for adjusting FPGA bus delay

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Experimental program
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specific Embodiment 1

[0069] This embodiment is a preferred implementation of the method for adjusting FPGA bus delay in the present invention, and the specific process is as follows figure 1 shown, including:

[0070] 1. Divide the interconnection bus between the master FPGA and the slave FPGA into at least one group;

[0071] In this embodiment, the interconnection bus is divided into 3 groups according to the interface type of the interconnection bus, bus 1, bus 2 and bus 3, and the buses of the same interface type are divided into one group;

[0072] 2. The main FPGA selects a group of buses;

[0073] 3. The main FPGA inverts the state of all signal lines of the group bus;

[0074] 4. When the signal on any one of the signal lines of the group of buses detected by the FPGA is reversed, record the signals on all the signal lines of the group of buses detected by the FPGA;

[0075] 5. Determine whether there is a signal line that has not detected a state inversion;

[0076] 501. The slave FPG...

specific Embodiment 2

[0086] This embodiment is another preferred embodiment of the method for adjusting FPGA bus delay of the present invention, and the overall process is as follows figure 2 shown, including:

[0087] Steps 1~4 are identical with specific embodiment 1;

[0088] 5. Judging from the FPGA whether the signal detected by the signal line has not been reversed, if there is a signal detected by the signal line, the signal has not been reversed, and then go to step 6, otherwise go to step 7;

[0089] 6. If there is no inversion of the signal detected by the signal line, select an FPGA among the master FPGA and the slave FPGA whose delay of all the pins of the bus in this group has not reached the maximum value set by the system, and set all the pins in the selected FPGA. The pin corresponding to the signal line with the correct received signal is delayed by one delay unit; return to step 3;

[0090] 611. Determine from the FPGA whether there is a pin whose delay has reached the maximum...

specific Embodiment 3

[0109] This embodiment is another preferred embodiment of the method for adjusting FPGA bus delay of the present invention, and the overall process is as follows figure 2 shown, including:

[0110] Steps 1~5 are identical with specific embodiment 1;

[0111] 6. If there is no inversion of the signal detected by the signal line, select an FPGA among the master FPGA and the slave FPGA whose delay of all the pins of the bus in this group has not reached the maximum value set by the system, and set all the pins in the selected FPGA. The pin corresponding to the signal line with the correct received signal is delayed by one delay unit; return to step 3;

[0112] 621. The main FPGA judges whether there is a pin whose delay has reached the maximum value set by the system in the group of bus pins; if there is, execute step 622, otherwise execute step 627;

[0113] 622, the master FPGA sends a signal to the slave FPGA through the selected bus; the sending signal is to invert the sta...

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Abstract

The invention discloses a method for adjusting FPGA bus delay, comprising: the master FPGA sends a signal to the slave FPGA through the bus; when the slave FPGA detects a signal on any signal line, record all the signals of the group bus detected from the FPGA The signal on the line; determine whether there is a signal line that has not detected a state inversion; if there is a signal line that has not detected a state inversion, the delay of all pins of a bus selected from the master FPGA and the slave FPGA has not reached the system setting. For the FPGA with the maximum value, delay the pins corresponding to the correct signal lines of all received signals in the selected FPGA by one delay unit, otherwise record the delay unit data of all pins of the master FPGA and slave FPGA. The invention also discloses an FPGA bus delay adjustment device adapted to the method. The technical scheme of the invention realizes automatic adjustment of the delay unit data of each pin of the bus, and improves the FPGA bus delay adjustment efficiency.

Description

technical field [0001] The invention relates to a field programmable gate array (FPGA for short) prototype verification system construction technology, in particular to a method and device for adjusting FPGA bus delay. Background technique [0002] FPGA prototyping is a methodology for building system-on-chip (abbreviation, SoC) and application-specific integrated circuit (abbreviation, ASIC) design prototypes on FPGA, which can facilitate hardware verification and early software development. This methodology is also known as ASIC prototyping or SoC prototyping. [0003] System prototyping is a new key factor for SoC success. As SoC designs become more and more complex, designers find it difficult to verify the correctness of hardware design only by software simulation due to the limitation of simulation speed and modeling. Running SoC design on FPGA prototype is a reliable method to verify the correctness of hardware design, and the operating frequency of the prototype ve...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F13/40G01R31/02
Inventor 高峰王明耀
Owner SPREADTRUM COMM (SHANGHAI) CO LTD