Method for fabricating a semiconductor power device

Abstract

The present invention provides a method for fabricating a power device. A first conductive substrate is provided, and a conductive epitaxial layer is formed on conductive substrate substrate. Then a pad layer and a hard mask are formed on the first conductive epitaxial layer. At least a trench is etched into the hard mask, the pad layer, and the first conductive epitaxial layer. The hard mask is removed and a buffer layer is formed at the sidewall of the trench. The trench is then filled with a dopant source layer comprising plural dopants. A drive-in process is performed to diffuse the second conductive dopants into the first conductive epitaxial layer through the buffer layer, thereby forming a second conductive diffusion region.

Description

technical field [0001] The invention relates to the technical field of power semiconductor devices, in particular to a method for manufacturing a power metal oxide semiconductor field-effect transistor (power MOSFET) device with a super-junction. Background technique [0002] Power semiconductor devices are often used in power management, such as switching power supply, computer center or peripheral power management IC, backlight power supply or motor control, etc., and its types include insulated gate bipolar transistors (insulated gate bipolar transistor (IGBT), metal-oxide-semiconductor field effect transistor (MOSFET) and bipolar junction transistor (bipolar junction transistor, BJT) and other devices. Among them, MOSFETs are widely used in various fields because they can save power and provide faster device switching speeds. [0003] In a power device, the design of the substrate is that P-type epitaxial layers and N-type epitaxial layers are arranged alternately, so t...

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Problems solved by technology

For example, by the above method of etching the epitaxial layer, a flat surface cannot be produced on the sidewall of the trench, so the contact surface between the first conductivity type epitaxial layer and the second conductivity type epitaxial layer cannot be a flat surface, and even the first conductivity type epitaxial layer cannot be flat. Type epitaxial layer and the contact surface of the second conductivity type epitaxial layer will have incomplete contact

Causes the junction of the depletion region produced by the epitaxial layer of the first conductivity type and the epitaxial layer of the second conductivity type to be uneven, further reducing the withstand voltage capability of the super interface

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