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Preparation process of dual damascene shallow dummy metal

A technology of redundant metal and preparation process, which is applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve incompatibility and other problems, and achieve the effect of reducing parasitic capacitance, simple process and increasing process steps

Inactive Publication Date: 2012-11-14
SHANGHAI HUALI MICROELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, the current method of making shallow redundant metal by adding an independent redundant metal mask is not compatible with the metal hard mask partial trench-first dual damascene process.

Method used

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  • Preparation process of dual damascene shallow dummy metal
  • Preparation process of dual damascene shallow dummy metal
  • Preparation process of dual damascene shallow dummy metal

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Embodiment Construction

[0039] The double damascene shallow redundant metal manufacturing process proposed by the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. Advantages and features of the present invention will be apparent from the following description and claims. It should be noted that all the drawings are in very simplified form and use imprecise ratios, which are only used for the purpose of conveniently and clearly assisting in describing the embodiments of the present invention.

[0040] The core idea of ​​the present invention is to provide a double damascene shallow redundant metal manufacturing process, by adding redundant metal patterns on the through-hole photomask, using metal-dielectric layer-metal as part of the groove of the hard mask. The double damascene process forms a double damascene structure with shallow redundant metal, which can reduce the parasitic capacitance of the metal interconnectio...

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Abstract

The invention discloses a manufacture process of dual damascene shallow dummy metal. According to the process, a dummy metal pattern is added to a through hole photomask, and a dual damascene structure with shallow dummy metal is formed by adopting a partial groove optimized dual damascene process by taking metal-dielectric layer-metal as a hard mask, so that metallic interconnected parasitic capacitors can be reduced, the chemical mechanical polishing (CMP) process cannot be deteriorated while the interconnected RC (resistor capacitor) delay is improved. The manufacture process is simple, does not increase process steps, and can be completely compatible with hard mask partial groove optimized dual damascene manufacture process.

Description

technical field [0001] The invention relates to the technical field of semiconductor technology, in particular to a double damascene shallow redundant metal preparation technology. Background technique [0002] With the continuous reduction of the feature size of semiconductor integrated circuits, the delay of the resistor capacitor (RC) in the back-end interconnection shows a significant increase trend. In order to reduce the RC delay of the back-end interconnection, a low dielectric constant (Low-k ) material, and copper interconnection replaces aluminum interconnection to become the mainstream process. Since copper interconnects cannot be formed by etching metal layers like aluminum interconnects, the copper damascene process has become the standard method for copper interconnects. [0003] The copper damascene process is: depositing a dielectric layer on a planar substrate; forming inlaid vias and trenches in the dielectric layer by photolithography and etching processe...

Claims

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Application Information

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IPC IPC(8): H01L21/768
Inventor 李磊梁学文胡友存陈玉文姬峰
Owner SHANGHAI HUALI MICROELECTRONICS CORP
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