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Semiconductor structure and preparation method thereof

A semiconductor and body contact technology, which is applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve the problem of non-existence of heterogeneous semiconductor structures, and achieve the effect of reducing defects and improving performance during heterogeneous epitaxy

Active Publication Date: 2014-09-17
BEIJING YANDONG MICROELECTRONICS
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0008] However, currently no efficient process exists to incorporate selective SOI technology in heterogeneous semiconductor structures

Method used

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  • Semiconductor structure and preparation method thereof
  • Semiconductor structure and preparation method thereof
  • Semiconductor structure and preparation method thereof

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Embodiment Construction

[0024] Hereinafter, the present invention is described by means of specific embodiments shown in the drawings. It should be understood, however, that these descriptions are exemplary only and are not intended to limit the scope of the present invention. Also, in the following description, descriptions of well-known structures and techniques are omitted to avoid unnecessarily obscuring the concept of the present invention.

[0025] A schematic diagram of a layer structure according to an embodiment of the invention is shown in the drawing. The figures are not drawn to scale, with certain details exaggerated and possibly omitted for clarity. The shapes of the various regions and layers shown in the figure, as well as their relative sizes and positional relationships are only exemplary, and may deviate due to manufacturing tolerances or technical limitations in practice, and those skilled in the art will Regions / layers with different shapes, sizes, and relative positions can be...

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Abstract

The invention discloses a semiconductor structure and a preparation method thereof. The method comprises that a first semiconductor layer is provided, a dielectric material layer is arranged on the first semiconductor layer, an opening is limited in the dielectric material layer, a second semiconductor layer grows on the first semiconductor layer in an epitaxial growth mode via the opening, is filled in the opening and covers the dielectric material layer, the material of the second semiconductor layer is different from the material of the first semiconductor layer, an insulation region is formed on the second semiconductor layer, then at least one selective silicon on insulator (SOI) region is limited, the selective SOI region comprises SOI parts and a body contact part, the body contact part is sandwiched between the SOI parts, the SOI parts are located on the dielectric material layer, and the body contact body is located on the first semiconductor layer. According to the semiconductor structure and the method, a heterogeneous selective SOI structure is provided, growth defects of heteroepitaxy is reduced, and the selective SOI configuration also can be achieved.

Description

technical field [0001] The invention relates to the field of semiconductors, in particular to a heterogeneous semiconductor structure including a selective semiconductor-on-insulator (SOI) configuration and a manufacturing method thereof. Background technique [0002] Generally speaking, heteroepitaxy refers to the epitaxial growth of another crystalline material on a crystalline material, such as the epitaxial growth of germanium (Ge), III-V compound semiconductors, etc. on a silicon (Si) substrate. With the continuous development of semiconductor technology, heteroepitaxy technology has become more and more important. For example, depositing Ge with high carrier mobility on a Si substrate as a channel region material can form a high-performance Ge channel Metal Oxide Semiconductor Field Effect Transistor (MOSFET). In addition, deposition of materials such as III-V compound semiconductors on Si substrates facilitates the integration of optoelectronic devices with Si comple...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/762H01L21/336H01L29/78H01L29/06
Inventor 骆志炯尹海洲朱慧珑
Owner BEIJING YANDONG MICROELECTRONICS