Wafer level chip scale package (WLCSP) single chip packaging piece and plastic packaging method thereof

A packaging method and packaging technology, which is applied in the direction of electrical components, electrical solid-state devices, semiconductor devices, etc., can solve the problems of high cost, complicated WLCSP manufacturing process, and extremely high precision requirements for electroplating and photolithography

Inactive Publication Date: 2012-12-26
HUATIAN TECH XIAN
View PDF3 Cites 2 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0010] The traditional WLCSP production process is complicated, and the precisio

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Wafer level chip scale package (WLCSP) single chip packaging piece and plastic packaging method thereof

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0037] A WLCSP single-chip package, plated with Au or Cu metal bumps 4 and a tin layer 2, its packaging method: follow the steps below:

[0038] The first step, wafer thinning;

[0039] The thinned thickness of the wafer is 50μm, and the roughness Ra is 0.10mmmm;

[0040] The second step is to plate metal bumps;

[0041] Plating metal bumps 4 on the surface of metal Au in the chip nip area on the entire wafer;

[0042] The third step, scribing;

[0043] For wafers with a thickness below 150 μm, use a double-knife dicing machine and its process;

[0044] The fourth step is to tin-plate the corresponding area of ​​the frame;

[0045] A layer of 2um tin layer 2 is plated on the corresponding area of ​​the PAD on the pin 1 in the frame;

[0046] The fifth step, core;

[0047] Turn the IC chip 5 upside down, and weld the metal bumps 4 on the IC chip 5 to the frame by using the Flip-Chip process;

[0048] The sixth step, reflow soldering;

[0049] Using the reflow soldering ...

Embodiment 2

[0053] A WLCSP single-chip package, coated with Cu metal bumps 4 and tin layer 2, its packaging method: follow the steps below:

[0054] The first step, wafer thinning;

[0055] The thickness of wafer thinning is 130μm, and the roughness Ra is 0.20mm;

[0056] The second step is to plate metal bumps;

[0057] Plating metal bumps 4 on the metal Cu surface of the chip nip area on the entire wafer;

[0058] The third step, scribing;

[0059] For wafers with a thickness below 150 μm, use a double-knife dicing machine and its process;

[0060] The fourth step is to tin-plate the corresponding area of ​​the frame;

[0061] A layer of 25um tin layer 2 is plated on the corresponding area of ​​PAD on pin 1 in the frame;

[0062] The fifth step, core;

[0063]Turn the IC chip 5 upside down, and weld the metal bumps 4 on the IC chip 5 to the frame by using the Flip-Chip process;

[0064] The sixth step, reflow soldering;

[0065] Using the reflow soldering process after SMT, afte...

Embodiment 3

[0069] A WLCSP single-chip package, plated with Au or Cu metal bumps 4 and a tin layer 2, its packaging method: follow the steps below:

[0070] The first step, wafer thinning;

[0071] The thickness of wafer thinning is 200μm, and the roughness Ra is 0.30mm;

[0072] The second step is to plate metal bumps;

[0073] Plating metal bumps 4 on the surface of metal Al or Cu in the chip nip area on the entire wafer;

[0074] The third step, scribing;

[0075] Wafers above 150μm adopt ordinary dicing process;

[0076] The fourth step is to tin-plate the corresponding area of ​​the frame;

[0077] A layer of 50um tin layer 2 is plated on the corresponding area of ​​PAD on pin 1 in the frame;

[0078] The fifth step, core;

[0079] Turn the IC chip 5 upside down, and weld the metal bumps 4 on the IC chip 5 to the frame by using the Flip-Chip process;

[0080] The sixth step, reflow soldering;

[0081] Using the reflow soldering process after SMT, after tin melting treatment, ...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

PUM

No PUM Login to view more

Abstract

The invention relates to a wafer level chip scale package (WLCSP) single chip packaging piece and a plastic packaging method thereof and belongs to the technical field of integrated circuit (IC) packaging. Tin layers are plated on pins inside a frame and a metal protruded point area, metal protruded points are plated on a pressure area surface of an IC chip, and the metal protruded points and the tin layer on the pins inside the frame are soldered by solder in a flip-chip method. The pins inside the frame are sequentially the tin layers, the solder, the metal protruded points and the IC chip. A plastic package body surrounds the pins inside the frame, the tin layers, the solder, the metal protruded points and the IC chip to form circuit integrity. The IC chip, the metal protruded points, the solder, the tin layers and the pins inside the frame form power and signal paths of a circuit. By adopting the metallic coating protruded point different from the past and the solder to weld the chip with frame pins, in the process of bonding, routing is not needed, and therefore breakover and mutual connection between the chip and the pins can be achieved directly. Thus, the WLCSP single chip packaging piece and the plastic packaging method thereof have the advantages of being low in cost and high in efficiency.

Description

technical field [0001] The invention relates to a WLCSP single-chip package and a plastic sealing method thereof. The WLCSP single-chip package is plated with Au or Cu metal bumps and a tin layer, and belongs to the technical field of integrated circuit packaging. Background technique [0002] With the rapid development of microelectronics technology and the increase in the complexity of integrated circuits, most of the functions of an electronic system may be integrated in a single chip (system on chip), which requires microelectronic packages to have higher performance and more More leads, denser interconnection, smaller size or larger chip cavity, greater heat dissipation function, better electrical performance, higher reliability, lower cost per lead, etc. The chip packaging process has changed from chip-by-chip packaging to wafer-level packaging. Wafer-level chip packaging technology——WLCSP just meets these requirements and forms a compelling WLCSP process. [0003] Wa...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

Application Information

Patent Timeline
no application Login to view more
IPC IPC(8): H01L23/495H01L21/60
CPCH01L2224/16245
Inventor 郭小伟谌世广崔梦谢建友刘卫东
Owner HUATIAN TECH XIAN
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products