Isolated gate controlled transverse field emission transistor and driving method thereof

Abstract

The invention relates to an isolated gate controlled transverse field emission transistor and a driving method thereof. The transistor comprises a first gate dielectric layer, a first gate electrode, a collector electrode and an emitter electrode, wherein the first gate dielectric layer is provided with a first surface and a second surface which are opposite to each other; the first gate electrode is arranged on a first surface of the first gate dielectric layer; the collector electrode and the emitter electrode are arranged on a second surface of the first gate dielectric layer and at both sides of the first gate electrode; and the collector electrode and the emitter electrode are insulated from each other, and a gas is formed between the collector electrode and the emitter electrode. According to the invention, electric conduction is realized through a field emission current from the emitter electrode to the collector electrode in the field effect transistor, and a current switch of transverse field emission from the emitter electrode to the collector electrode is controlled by the first gate electrode at the same time, so that limitation in carrier transport by a lattice structure of a channel region in a conventional MOS ( field effect transistor) is eliminated, the need of process development can be met, and the transistor has a higher response speed.

Description

technical field [0001] The invention relates to the field of semiconductor devices, in particular to an insulated gate-controlled lateral field emission transistor and a driving method thereof. Background technique [0002] With the development of semiconductor technology and the continuous reduction of critical dimensions (CD, Critical Dimension), the challenges faced by conventional MOS field effect transistors are becoming more and more severe. For conventional MOS field effect transistors, the movement modes of carriers in the channel mainly include drift, diffusion and scattering. In order to improve carrier mobility, the current mainstream technology is strained silicon technology, which mainly introduces stress, such as tensile stress or compressive stress, to the channel region of MOS transistors, thereby changing the lattice structure of the channel region and improving the current carrying capacity. sub-transport efficiency. [0003] However, with the further red...

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Problems solved by technology

[0003] However, with the further reduction of the device size, the channel length of the MOS field effect transistor becomes very small, and the ejection movement of the carriers in the short-distance channel lattice becomes more and more significant, so that the strained silicon technology is also Will encounter a bottleneck, both carrier mobility and current density will be significantly affected

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