Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

High-speed fixed point fast fourier transformation (FFT) processor based on field programmable gate array (FPGA) and processing method for high-speed fixed point FFT processor

A processor and high-speed technology, applied in the direction of complex mathematical operations, etc., can solve the problems of FFT processor control logic complexity, low operating frequency, long processing delay, etc., to achieve improved operating frequency and data processing speed, short design cycle, hardware high cost effect

Inactive Publication Date: 2015-06-17
XIDIAN UNIV
View PDF7 Cites 1 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0007] The purpose of the present invention is to overcome above-mentioned deficiencies in the prior art, solve the traditional FFT processor control logic complexity, processing delay is longer, the problem of lower working frequency, has proposed a kind of high-speed fixed-point FFT processor based on FPGA, and adopts pipeline The structural method realizes fast and high-precision FFT operation processing of data

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • High-speed fixed point fast fourier transformation (FFT) processor based on field programmable gate array (FPGA) and processing method for high-speed fixed point FFT processor
  • High-speed fixed point fast fourier transformation (FFT) processor based on field programmable gate array (FPGA) and processing method for high-speed fixed point FFT processor
  • High-speed fixed point fast fourier transformation (FFT) processor based on field programmable gate array (FPGA) and processing method for high-speed fixed point FFT processor

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0040] The FFT processor of the present invention will be further described below in conjunction with the accompanying drawings.

[0041] Refer to attached figure 1, the FFT processor of the present invention includes a multi-level FFT processing module and a first-level inversion sequence output module. The FFT processing module and the inversion sequence output module are cascaded through the data bus and the control bus according to the pipeline mode, and the cascading number of the multi-stage FFT processing modules is determined by the length of the data sequence processed by the FFT processor. In this embodiment, the FFT processing module The number of cascades is 10. The FFT processing module receives the input data from the previous FFT processing module or the FFT operation, performs butterfly processing on the input data, performs two butterfly processing on four corresponding data in each clock cycle, and outputs the processing results to A next-level FFT processi...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention discloses a high-speed fixed point fast fourier transformation (FFT) processor based on a field programmable gate array (FPGA) and a processing method for the high-speed fixed point FFT processor. The FFT processor comprises a multi-stage FFT processing module and a one-stage bit-reversed order output module. The processing method comprises the following steps of: 1, receiving data; 2, turning the data; 3, storing the data and performing disk-type processing on the data; 5, judging whether calculation is finished or not; 6, adjusting the position of the processed data; 7, storing the adjusted data; and 8, outputting a bit-reversed order. By adopting a pipeline architecture and a multi-data parallel processing method, high-speed and high-precision FFT calculation is realized; the shortcomings of long design period and high hardware cost of the conventional FFT processor based on a digital signal processor (DSP) and the shortcoming that the conventional FFT processor cannot process the data in parallel are overcome; and the working frequency and the data processing rate of the FFT processor are improved.

Description

technical field [0001] The present invention relates to the technical field of digital signal processing, and further relates to high-speed fixed-point Fast Fourier Transform (FFT) processing based on Field Programmable Gate Array (Field Programmable Gate Array, FPGA) in the technical field of communication and radar signal processing devices and their processing methods. The invention can improve the data processing rate and system performance when the data is processed in real time by fast Fourier transform in the field programmable gate array. Background technique [0002] There are many ways to realize FFT operation, which can be realized by software or by hardware. Since general software runs on large computing devices such as PCs or servers, its calculation speed is very slow, and the equipment is bulky, which cannot meet the requirements of fast and portable FFT processing in radar, signal analysis and other application fields. Therefore, the implementation of FFT g...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Patents(China)
IPC IPC(8): G06F17/14
Inventor 史江义舒浩谢辉辉马佩军田映辉邸志雄汤海华
Owner XIDIAN UNIV
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products