Power transistor manufacture method

Abstract

The invention discloses a power transistor manufacture method. By the method, insulating medium layers formed on the top of gate polycrystalline silicon and spacer medium layers formed on the side faces of the insulating medium layers serve as hard masks for etching a pressure-bearing region, so that the number of masks required by the front-side process is decreased, and the density of transistors in a chip can be increased. By the aid of the method, a trench is formed in a P-type well region by etching, and a P-type polycrystalline silicon layer and an N-type polycrystalline silicon layer are filled inside the trench and subjected to annealing to promote formation of a source electrode and a back gate contact region which are longitudinally distributed, so that latching resistance of devices can be improved, and power devices lower in breakover resistance and saturation voltage drop and higher in current driving capacity can be obtained beneficially.

Description

technical field [0001] The invention relates to a manufacturing process method of a semiconductor integrated circuit, in particular to a manufacturing method of a power transistor. Background technique [0002] In the application of power and high-voltage devices, it is hoped that the on-resistance of the transistor will be smaller, the saturation voltage drop will be lower, and the current driving capability will be greater. How to integrate more devices within a certain chip area is particularly important. However, the alignment deviation between different masks makes the device size unable to be reduced according to the demand, and the more precise photolithography technology makes the manufacturing cost expensive, which is not conducive to mass production. In addition, when the hole current in the well region reaches a certain level, the potential of the well region will be raised, and the source-well junction barrier will be lowered, causing the parasitic bipolar transi...

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Problems solved by technology

However, the alignment deviation between different masks prevents the size of the device from being reduced according to demand, and the more precise photolithography technology makes the manufacturing cost expensive, which is not conducive to mass production.

In addition, when the hole current in the well region reaches a certain level, the potential of the well region will be raised, and the source-well junction barrier will be lowered, causing the parasitic bipolar transistor to be turned on. At this time, the gate cannot control the current switch, and a latch occurs effect

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