Semiconductor device and manufacture method thereof

Abstract

The invention relates to a semiconductor device and a manufacture method thereof. The semiconductor device comprises a P-channel semiconductor and an N-channel semiconductor, and the manufacture method of the semiconductor device includes the steps: forming a gate electrode dielectric layer on a substrate; forming a gate electrode material layer on the gate electrode dielectric layer; performing blanket type pre-doping for introducing N-type dopant for the gate electrode material layer; and performing fluorine pre-doping for an area, used for the P-channel semiconductor, of the gate electrode material layer so that F can be introduced into an interface between the substrate and an area, used for the P-channel semiconductor, of the gate electrode dielectric layer. The gate electrode material layer comprises an area used for the N-channel semiconductor. Part of P-type impurities in P-type F-containing dopant are used for counteracting the influences of the introduced N-type dopant on the gate electrode material layer, while the other part of the P-type impurities in the P-type F-containing dopant are used for depletion of the PMOS (P-channel metal oxide semiconductor) gate electrode material layer.

Description

technical field [0001] The invention relates to the field of semiconductor technology, in particular to a semiconductor device and a manufacturing method thereof. Background technique [0002] As Ultra Large Scale Integration (ULSI) continues to shrink, the thickness of the gate dielectric of MOS (Metal-Oxide-Semiconductor) devices also continues to decrease to achieve higher device performance. However, the threshold voltage Vt of the device is limited and cannot be reduced infinitely. Currently, the gate voltage Vg is about 1.0V, which has reached the bottleneck. [0003] A relatively large percentage reduction in gate dielectric layer thickness and a relatively small percentage reduction in threshold voltage lead to negative bias temperature instability (NBTI) performance degradation of the device, thereby failing to comply with specified requirements. As is well known to those skilled in the art, the negative temperature deviation instability refers to the performance ...

AI Technical Summary

Problems solved by technology

[0006] However, pure F implantation can cause bubble defects at very high doses

That is to say, the dose of F is limited when using pure F implantation method, therefore, the improvement of NBTI performance by F implantation is limited

Images