Manufacturing method of semiconductor devices

Abstract

The invention discloses a manufacturing method of semiconductor devices. The manufacturing method includes steps of a), providing a semiconductor substrate with an NMOS(N-channel metal oxide semiconductor) transistor and a PMOS(P-channel metal oxide semiconductor) transistor; b), forming a stress capping layer on the NMOS transistor, the PMOS transistor and the semiconductor substrate; c), doping Ge in the stress capping layer covering the PMOS transistor; and d), annealing. Since the capping layer is formed on the NMOS transistor and the PMOS transistor simultaneously, and stress is released by Ge doped in the stress capping layer covering the PMOS transistor, carrier mobility of trench areas of the NMOS transistor is improved and electrical performance of the NMOS transistor is improved while affection to electrical performance of the PMOS transistor is avoided on the premise of reduction of processing steps. Besides, compared with the prior art, the manufacturing method has the advantages that processing steps are reduced evidently, production cycle is shortened, and running cost is reduced.

Description

technical field [0001] The invention relates to a semiconductor manufacturing process, in particular to a method for manufacturing a semiconductor device. Background technique [0002] With the development of semiconductor technology to 65nm technology node or even smaller, stress technology has been used in CMOS process to improve the performance of semiconductor devices. Stress Memorization Technology (SMT), as a widely used stress technology, is used to improve the performance of NMOS devices. [0003] In the traditional SMT process, stress layer deposition and source / drain annealing process are usually used to induce stress in the substrate and improve the carrier mobility in the channel of the NMOS device, thereby improving the electrical performance of the NMOS device. Figures 1A-1H It is a schematic diagram of each step in the process of manufacturing a semiconductor device using an SMT process in the prior art. [0004] Such as Figure 1A As shown, a semiconductor...

AI Technical Summary

Problems solved by technology

In an actual process, the thickness of the buffer oxide layer 207 in the PMOS region is about 55-65 angstroms smaller than the thickness of the buffer oxide layer 207 in the NMOS region, which is not conducive to the subsequent processing process.

[0013] In addition, the above-mentioned process of manufacturing semiconductor devices using the SMT process is complicated, thus prolonging the product production cycle and increasing the operating cost

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