Method for forming copper Damascus structure

Abstract

The invention provides a method for forming a copper Damascus structure. The method comprises steps of depositing an interlayer dielectric and a sacrifice layer on a substrate, and graphing photosensitive resist; regarding the graphed photosensitive resist as a mask, etching the interlayer dielectric and the sacrifice layer and forming a metal interconnection line groove; depositing a barrier layer and a metal interconnection line in the groove sequentially; and removing excess copper, the sacrifice layer and the barrier layer through the chemical mechanical planarization process and finally forming the copper Damascus structure. Therefore, by the aid of the method, the sacrifice layer is deposited on the interlayer dielectric, a prior dielectric anti-reflection coating is replaced, the standing wave effect of the photosensitive resist is reduced, and the lithographic performance is improved. The sacrifice layer serves as a sacrifice layer of the etching process, the loss of the interlayer dielectric in the copper Damascus structure is reduced, the thickness of the metal interconnection line is increased, is stable and can be controlled, and the controllability and the stability of wafer electrical properties can be improved.

Description

technical field [0001] The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a method for forming a copper damascene structure. Background technique [0002] With the continuous reduction of the size of semiconductor integrated circuits, in order to reduce the signal crosstalk and RC delay of integrated circuits, in the semiconductor chip manufacturing industry, copper with lower resistivity is often used instead of aluminum as metal interconnection lines. However, since the copper interconnection cannot be dry-etched, a chemical mechanical planarization (CMP) method is usually used to remove excess copper to form the copper interconnection. [0003] At present, in the process of planarizing copper by CMP process, a polishing liquid is often used to simultaneously remove the barrier layer and the dielectric anti-reflection coating. However, during the removal process, copper damascene structures can result due to differences ...

AI Technical Summary

Problems solved by technology

However, CMP-based barrier polishes do not have a good polishing selectivity ratio for interlayer dielectrics and dielectric antireflective coatings.

Therefore, the interlayer dielectric loss 207 will be caused during the chemical mechanical polishing process, such as Figure 7 shown

Due to the loss of the interlayer dielectric, the thickness of the copper metal interconnection in the interlayer dielectric is reduced, resulting in electrical defects such as high resistivity of the wafer and poor leakage performance.

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