An electro-static discharge protection circuit for an integrated circuit and a manufacturing method thereof

Abstract

The present invention discloses an electro-static discharge protection circuit for an integrated circuit and a manufacturing method thereof. The protection circuit includes a GGMOS and at least one through-silicon via which share the same substrate; and the silicon via is arranged in the substrate around the GGMOS. In the electro-static discharge protection circuit for the integrated circuit of the present invention, when the ESD (electro-static discharge) is produced, heat will be generated on the GGMOS due to the presence of the ESD current; by using the silicon via disposed in the substrate around the GGMOS, better and faster heat dissipation for the GGMOS can be achieved, thus preventing damage to the GGMOS caused by heat, and extending the service life of the electro-static discharge protection circuit; and GGMOS turn-on voltage adjustment can also be achieved by arrangement mode of silicon vias at the same time. According to the protection circuit, the size of the GGMOS is reduced, so that the entire region GGMOS is enabled to be completely open when the ESD is produced, thereby improving utilization rate of the GGMOS.

Description

technical field [0001] The invention relates to semiconductor manufacturing technology, in particular to an integrated circuit electrostatic discharge protection circuit and a manufacturing method thereof. Background technique [0002] ESD (Electro-Static discharge, electrostatic discharge) is a rapid neutralization process of charges. Due to the high electrostatic voltage, ESD will bring destructive consequences to the integrated circuit, resulting in the failure of the integrated circuit. Therefore, in order to protect the integrated circuit from being damaged by ESD, an ESD protection circuit is also designed in the integrated circuit to prevent the integrated circuit from being damaged by ESD. [0003] In CMOS (Complementary Metal Oxide Semiconductor, Complementary Metal Oxide Semiconductor) technology, NMOS (N-Metal-Oxide-Semiconductor, N-type Metal Oxide Semiconductor) devices include parasitic lateral npn transistors. At present, GGNMOS (Gate Grounded NMOS, gate gro...

AI Technical Summary

Problems solved by technology

In an ideal state, when a certain moment is reached, the entire multi-finger GGNMOS circuit can be turned on, but the ESD current conducted by the middle part is still larger than the ESD current conducted by other parts, thus causing more heat. large, which can easily cause damage to the

However, in practical applications, the above-mentioned multi-finger GGNMOS circuit often only has an effect on the conduction of ESD current in the middle part, while the conduction effect of the edge part on the ESD current is negligible.

At the same time, due to the large conduction current in the middle part, the heat generated by it should not be dissipated quickly, which will easily cause premature aging of the device and reduce the service life of the integrated circuit.

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