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Etching method of gate sidewall layer on mos surface

A technology of gate sidewall layer and sidewall layer, which is applied in the direction of electrical components, semiconductor/solid-state device manufacturing, circuits, etc., can solve the problem of reducing MOS, doped region 5 damage, and source-drain doped region 5 morphology damage and other problems to achieve the effect of preventing etching and avoiding damage

Active Publication Date: 2015-12-16
SEMICON MFG INT (SHANGHAI) CORP
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  • Abstract
  • Description
  • Claims
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Problems solved by technology

However, whether it is a dry method or a wet method (usually phosphoric acid), it will cause the destruction of the morphology of the source-drain doped region 5, causing damage to the doped region 5 (such as the loss of the NiPtSi material in the doped region), such as image 3 As shown, thereby reducing the performance of MOS (MetalOxideSemiconductor, metal oxide semiconductor) devices

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  • Etching method of gate sidewall layer on mos surface
  • Etching method of gate sidewall layer on mos surface
  • Etching method of gate sidewall layer on mos surface

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Embodiment Construction

[0040] In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and examples.

[0041] Such as Figure 4 As shown, the etching method of the MOS surface gate sidewall layer provided by the present invention includes:

[0042] A MOS device is provided, the MOS device includes a substrate, a gate, a source and drain disposed on the substrate, and a sidewall layer disposed between the gate and the source and drain (source, drain);

[0043] Etching away part of the sidewall layer of the MOS device by dry method;

[0044]Carry out ozone water immersion to the MOS device after above-mentioned dry etching;

[0045] Wet etching is carried out on the MOS device after immersion in ozone water.

[0046] Wherein, the step of carrying out the step of ozone water immersion and the step of carrying out wet etching can adopt the mode that alter...

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Abstract

The invention discloses a method for etching a sidewall layer of a MOS (metal oxide semiconductor) surface gate. The method includes: providing an MOS device comprising a gate, a source, a drain and a sidewall layer, wherein the gate, the source and the drain are disposed on a substrate and the sidewall layer is between the gate and the source and drain; subjecting the MOS device to dry etching to remove part of the sidewall layer, subjecting the MOS device subjected to dry etching to ozone immersion; and subjecting the MOS device subjected to ozone immersion to wet etching. The part of the sidewall layer material is removed by the dry etching while a source and drain doped area is not destructed. A silicon oxide protecting film on the surface the doped area is formed by ozone immersion. During wet etching, phosphoric acid reacts with silicon oxide of the sidewall layer to remove the sidewall layer. The protecting film protects the doped area from being etched by the phosphoric acid. The ozone immersion and wet etching processes are alternate, so that the doped area is further protected. The doped area is protected while the sidewall layer is etched, so that damage of the performance of the MOS device is avoided.

Description

technical field [0001] The invention relates to semiconductor manufacturing technology, in particular to an etching technology on the surface of a MOS device. Background technique [0002] With the development of manufacturing technology, the size of transistors is getting smaller and smaller, and the performance is constantly improving. Among them, the strained silicon technology is indispensable, and currently the strained silicon technology is widely used in the field of semiconductor manufacturing. [0003] The semiconductor manufacturing industry generally agrees to use strained silicon technology to improve the performance of CMOS (Complementary Metal Oxide Semiconductor, Complementary Metal Oxide Semiconductor) devices. For example, applying tensile stress (Tensilestress) in the conductive channel of NMOS (N-Metal-Oxide-Semiconductor, N-type metal oxide semiconductor) devices can improve the electron mobility of NMOS; in PMOS (P-Metal-Oxide-Semiconductor , P-type me...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/336H01L21/311
Inventor 吴金刚刘焕新韦庆松何永根
Owner SEMICON MFG INT (SHANGHAI) CORP