Aqueous polishing composition and process for chemically mechanically polishing substrates containing silicon oxide dielectric and polysilicon films
A technology of water polishing and composition, applied in the field of new water-containing polishing compositions, to achieve the effects of improved process management, excellent global and local flatness, and improved selectivity
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[0130] The compositions of the present invention can be prepared without any particularity, but by dissolving or dispersing the abovementioned ingredients (A), (B) and (C) and optionally (D) and / or (E) in an aqueous medium, in particular performed in deionized water. For this purpose, customary and standard mixing methods and mixing equipment can be used, such as stirred tanks, in-line dissolvers, high-shear high-speed mixers, ultrasonic mixers, homogenizer nozzles or convective mixers. The composition of the invention thus obtained is preferably filterable through a filter having suitable mesh openings to remove coarse-grained particles such as agglomerates or aggregates of finely divided solid abrasive particles (A).
[0131] The compositions of the invention are well suited for the methods of the invention.
[0132] In the method of the invention, the substrate material of electronic, mechanical and optical devices, especially electronic devices, most preferably integrated...
Embodiment 1
[0149] Preparation of Aqueous Polishing Compositions 1-6
[0150] To prepare aqueous polishing compositions 1-6, cerium oxide (average particle size d as measured by dynamic laser light scattering) 50 120-140nm), polyethylene glycol (PEG 10K ; weight average molecular weight: 10,000) and sodium hexametaphosphate (PP; weight ratio of cerium oxide to PP=200, hereinafter referred to as PP 200 ) dispersed or dissolved in ultrapure water. The amounts used are summarized in Table 1.
[0151] Table 1: Composition of Aqueous Polishing Compositions 1-6
[0152] Composition number
[0153] 4 (comparative example)
Embodiment 2 and 3 and comparative Embodiment C1-C4
[0155] CMP of a polysilicon layer on a silicon semiconductor wafer
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