Data erasing circuit for non-volatile memory

Abstract

The invention provides a data erase circuit of a nonvolatile memory. The circuit comprises a charge pump, a high voltage detection circuit, a level conversion circuit, a bias circuit, an inverter circuit, a signal generating circuit, a latch circuit, and an erase control circuit. The erase control circuit inputs a first selection signal and a second selection signal, and outputs a word line strobe signal. When the first selection signal is in high level and the second selection signal is in low level, the word line strobe signal is connected to an erase power supply signal; a memory unit corresponding to the word line strobe signal is selected, and data erasing operation is executed. When the first selection signal is in low level and the second selection signal is in high level, the word line strobe signal is connected to a first bias signal; the memory unit corresponding to the word line strobe signal is not selected, and data erasing operation is not executed. The nonvolatile memory data erase circuit provided by the invention has the advantages of low generated leakage current, low power consumption, stable performance, and the like.

Description

technical field [0001] The invention relates to the field of integrated circuit design, in particular to a data erasing circuit of a non-volatile memory. Background technique [0002] For non-volatile memory such as FLASH MEMORY and Electrically Erasable Programmable Read-Only Memory (EEPROM), in order to reuse the storage space of its storage unit, it is generally necessary to first erase the original data of the storage unit. After that, new data is stored in the storage unit of the non-volatile memory. The memory cell structure generally adopts a determinant matrix, that is, a determinant matrix composed of word lines in the row direction and word lines in the column direction. The memory cell structure generally adopts a determinant matrix, that is, a determinant matrix composed of word lines in the row direction and bit lines in the column direction. The data erasing operation of the memory cell is to erase the data on the memory cell corresponding to the word line by...

AI Technical Summary

Problems solved by technology

[0006] To sum up, the disadvantages of the data erasing circuit of the non-volatile memory in the prior art are that the generated leakage current is large and the power consumption is high

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