1.5t dynamic memory cell, array and operation method based on resistive switching gate dielectric

Abstract

The invention relates to the field of memory technology, and relates to a 1.5T dynamic memory unit based on a resistive gate dielectric, an array structure, and an operation method thereof. The invention includes: a transistor, including a source, a drain and a control gate; a storage node, that is, the gate dielectric of the transistor control gate, located between the transistor control gate and the silicon substrate, with storage resistance changes; a word line, Connected to the control gate of the transistor; the bit line is connected to the drain of the transistor; the source line is connected to the source of the transistor; among them, the read tube 201 plays the role of gating and current limiting, and 202 is used for programming Components, 203 is the bit line, 204 is the word line of 201, and 205 is the programming word line. The gate has different states of high resistance and low resistance, and the transition between them is reversible. When a certain voltage is applied between the bit line and the word line, there will be currents of different sizes. The invention solves the difficulties of the traditional 1T1C DRAM unit and the problem of poor compatibility with the standard CMOS process, and can be compatible with the standard logic CMOS HfOx high k metal gate technology.

Description

technical field [0001] The invention relates to the field of memory technology, in particular to a 1.5T dynamic memory unit based on a resistive variable gate medium, an array structure, and an operation method thereof. Background technique [0002] A storage cell of a traditional DRAM typically includes two elements, namely a storage capacitor and an access transistor, forming a 1T1C structure. See attached figure 1 , is a traditional DRAM array structure, where 100 to 108 are access transistors, 109 to 111 are bit lines, 112 to 114 are word lines, 115 to 117 are parasitic capacitances on bit lines, and 118 to 126 are storage capacitors . The working process of the traditional DRAM will be described below by taking the storage unit formed by operating the access transistor 100 and the storage capacitor 118 as an example. In the write operation phase, the data value is placed on the bit line 109, and the word line 112 is raised. According to the difference of the data val...

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Problems solved by technology

[0003] The purpose of the present invention is to solve the difficulty of traditional 1T1CDRAM unit scalingdown, and the problem of poor compatibility with standard CMOS technology, in view of this, the present invention provides a kind of 90nm and following node dynamic memory (especially embedded memory) A solution especially compatible with standard logic's CMOSHfOxhighkmetalgate technology

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