39results about How to "Improved data retention features" patented technology

To provide a semiconductor device having large memory capacity and high reliability of data or a small-size semiconductor device having a small circuit area. A memory cell includes first and second data retention portions capable of storing multilevel data. A data voltage is written to the first data retention portion from a first wiring through a transistor for reading the data voltage and a second wiring, and a data voltage is written to the second data retention portion from the second wiring through a transistor for reading the data voltage and the first wiring. With the configuration, data voltages reduced by the threshold voltages of the transistors for reading the data voltage can be retained in the first and second data retention portions. The written data voltages where the threshold voltages of the transistors are canceled can be read by precharging and then discharging the first wiring.

A semiconductor device having excellent data retention characteristics. A transistor with a low off-state current is utilized to save and retain data stored in a memory circuit, and a potential to be applied to a back gate of the transistor is applied from a battery provided for each memory circuit. The potential applied to the back gate of the transistor and a potential for charging the battery are generated in a voltage generation circuit. The battery is charged utilizing power gating of the memory circuit and data retention characteristics is improved.

An NOR memory based on a resistance-changeable gate dielectric comprises: a transistor comprising a source electrode, a drain electrode and a control gate electrode; a memory node which is a gate dielectric of the control gate electrode of the transistor, is positioned between the control gate electrode of the transistor and a silicon substrate and stores the resistance change; a word line connected to the control gate electrode of the transistor; a bit line connected to the drain electrode of the transistor; and a source line connected to the source electrode of the transistor. The gate electrode uses a resistance-changeable characteristic material having three different states of insulation, high resistance and low resistance, there is reversible switching between the high resistance and the low resistance, a constant voltage is applied among the word line, the source line and the bit line during reading, and "0" and "1" can be determined according to different currents. The invention also provides an array and an operation method of the NOR memory cell based on the resistance-changeable gate dielectric.

The invention belongs to the technical field of memories and relates to a 2T dynamic memory unit and array structure based on a resistance-change gate dielectric and a method for operating the same. The 2T dynamic memory unit and array structure comprises a write-in tube, a read tube, a memory part, a write word line, a write bit line, a read word line and a read bit line, wherein the source terminal of the write-in tube is connected with the gate electrode of the read tube; the write-in tube has a programming function; the gate dielectric of the read tube is the memory part; the gate dielectric has an insulation state, a high-resistance state and a low-resistance state, and the conversion between high resistance and low resistance is reversible; a certain voltage is applied to the gate electrode of the read tube and the read word line in a reading process; and '0'and '1' can be judged according to the voltage change or the current value of the read bit line. The 2T dynamic memory unit and array structure is simple and convenient in process, low in cost, superior in effect, low in power consumption and high in performance, and is compatible with the front end of a 32-nm High k CMOS logic process.

The invention belongs to the technical field of microelectronics and relates to a metal oxide non-volatile memory technique, in particular to a WOx-based resistance type memory and a preparation method thereof. The WOx-based resistance type memory comprises an upper electrode, a tungsten lower electrode and a WOx-based memory medium which is arranged between the upper electrode and the tungsten lower electrode; the WOx-based memory medium is formed by performing oxidation treatment on a WSI compound covered on the tungsten lower electrode; and x is more than 1 and less than or equal to 3. Theresistance type memory has the characteristics of improving the controllability of the process and the reliability of devices, along with relatively low power consumption and high data retention performance.

Provides a double gate memory cell having a silicon substrate with an active region having a channel region and source/drain regions, the active region forming a ridgelike fin with at least the channel region. A tunnel oxide layer is formed at least partly on the surface of the ridgelike fin of the active region. A floating gate for storing electrical charges is formed at least partly on the surface of the tunnel oxide layer. An intergate insulator layer made of a dielectric material is formed at least partly on the surface of the floating gate. A control gate is formed at least partly on the surface of the intergate layer, the tunnel oxide layer including an amorphous silicon dioxide/titanium dioxide mixed oxide.

The invention discloses a tungsten-titanium alloy nanocrystalline floating grid structure used for a flash memory, pertaining to the technical field of micro-electronics. The structure comprises a silicon substrate as well as a silicon oxide layer, a high k (dielectric constant) thin film, a tungsten-titanium alloy nanocrystalline charge storage layer, a barrier layer and a grid material layer which are covered on the silicon oxide layer successively. The structure improves memory properties of a non-volatile memory unit of the floating grid structure, such as programming/erasing efficiency, programming/erasing (P/E) speed, effective charge memory power, data maintenance property and programming/erasing tolerance. The invention also discloses a method for manufacturing the tungsten-titanium alloy nanocrystalline floating grid structure. The method is simple and convenient and is compatible with the traditional CMOS silicon planar technology.

The invention relates to the field of semiconductor charge capture memorizers, and discloses a nonvolatile double capture-silicon oxide nitride oxide semiconductor (SONOS) memorizer with a double layer dielectric charge capture layer. The nonvolatile DC-SONOS memorizer with the double layer dielectric charge trapping layer comprises a semiconductor substrate of a channel which is provided with a channel surface, a source terminal adjacent to the channel and a drain terminal adjacent to the channel, a grid electrode, a dielectric stack arranged between the grid electrode and the channel surface, and side walls arranged at two sides of the grid electrode and two sides of the dielectric stack. The dielectric stack comprises a tunneling layer contacted with the surface of the channel, a charge capture layer superimposed on the tunneling layer, the charge capture layer is of a double layer dielectric composite structure, a barrier layer superimposed on the charge capture layer, and the barrier layer is contacted with the grid electrode. The charge capture layer comprises a first layer dielectric contacted with the tunneling layer, wherein the first layer dielectric is made of Si3N4, the thickness of the first layer dielectric is 1-30, a second layer dielectric adjacent to the first layer dielectric, wherein the second layer dielectric is made of SiN, and the thickness of the second layer dielectric is 1-50. According to the DC-SONOS memorizer with the double layer dielectric charge capture layer, performance of traditional SONOS nonvolatile memorizers is improved, data-hold feature of the memorizer is improved, and the memorizer which is capable of keeping high data-hold feature under poor operating conditions is easy to obtain.

The invention belongs to the field of three-dimensional flash memory preparation, and more particularly to a three-dimensional nonvolatile semiconductor memory based on a nanocrystalline floating gateand a preparation method thereof. The three-dimensional semiconductor memory includes a plurality of three-dimensional NAND memory strings in a vertical direction, wherein each three-dimensional NANDmemory string includes a semiconductor region, and a four-layered package structure surrounding the semiconductor region and including a tunneling dielectric layer, a charge storage layer, a barrierdielectric layer and a control gate electrode; the material of the charge storage layer comprises a nanocrystalline material; and the nanocrystalline material is a sulfur-based compound nanocrystalline. The sulfur-based compound nanocrystalline having a high hole structure content is used as the material of the charge storage layer, thereby improving the programming/erasing efficiency, the programming/erasing speed, and the charge storage capability of a single memory cell of the three-dimensional flash memory. The process of the nanocrystalline floating gate of the invention is simple and iscompatible with a vertical channel process.