39results about How to "Improved data retention features" patented technology

A semiconductor memory device is comprised of a refresh counter for sequentially generating a count value indicating one or more row addresses corresponding to one or more word lines to be refreshed when receiving a refresh request at a predetermined interval in normal operation, in which the refresh counter includes n+1 stage counters assigned to n bits included in the row address and a dummy bit not included in the row address, and a counter portion from the least significant bit to the dummy bit forms an N-ary counter, so as to control whether or not refresh is performed in response to a value of the dummy bit when receiving the refresh request.

To provide a semiconductor device having large memory capacity and high reliability of data or a small-size semiconductor device having a small circuit area. A memory cell includes first and second data retention portions capable of storing multilevel data. A data voltage is written to the first data retention portion from a first wiring through a transistor and a second wiring, and a data voltage is written to the second data retention portion from the second wiring through a transistor and the first wiring. With the configuration, data voltages reduced by the threshold voltages of the transistors can be retained in the first and second data retention portions. The written data voltages where the threshold voltages of the transistors are canceled can be read by precharging and then discharging the first wiring.

The invention belongs to the technical field of memory, and relates to a 2T dynamic memory unit based on a resistive gate medium, an array structure and an operation method thereof. The present invention includes a write tube, a read tube, a storage unit, a write word line, a write bit line, a read word line, and a read bit line; the source end of the write tube is connected to the gate of the read tube, and the write tube It has the function of programming, and the gate medium of the reading tube is a storage part; the gate medium has three different states of insulation, high resistance, and low resistance, among which the transition between high resistance and low resistance is reversible, and when reading, it is read into the tube grid. A certain voltage is applied to the electrode and the read word line, and "0" and "1" can be judged according to the voltage change or current value of the read bit line. The invention has the advantages of simple process, low cost, superior effect, low power consumption and high performance, and is compatible with the front end of 32nm High k CMOS logic process.

A semiconductor device having silicon-oxide-nitride-oxide-silicon (SONOS) structure that overcomes spatial limitations which trap charges by not utilizing a flat, planar structure of the ONO film including a charging trap layer, thereby making it possible to improve reliability for data preserving characteristic of a SONOS device.

The invention belongs to the technical field of ferroelectric storage, in particular to a non-destructive readout ferroelectric memory, a preparation method and a read / write operation method thereof. The ferroelectric memory includes a ferroelectric thin film layer and a read-write electrode layer arranged on the ferroelectric thin-film layer. The read-write electrode layer is provided with a gap that divides it into at least two parts. The orientation direction is not substantially parallel to the normal direction of the read-write electrode layer; wherein, both the read operation and the write operation can be completed through the read-write electrode layer. The ferroelectric memory of the present invention is simple in structure, simple in preparation and low in cost, can realize non-destructive readout in current mode, and is suitable for high-density applications.

A semiconductor device is provided. An SRAM of the invention includes P-well regions PW_1 and PW_2, an N-well region NW, a first metal wire M1, and a second metal wire M2. The P-well regions PW_1 andPW_2 extend in a first direction, and pull-down transistors and accessing transistors are formed therein. The N-well region NW extends in first direction, and pull-up transistors are formed therein. The first metal wire M1 extends in the first direction on the N-well region NW and is electrically connected to the N-well region NW. The second metal wire M2 extends in a second direction orthogonal to the first direction and electrically connected to a common S / D region of a pair of pull-up transistors that are formed in the N-well region NW. The semiconductor can apply different voltages to sources and bases of pull-up transistors and improves write margin of memory cells.

The invention relates to the technical field of memories and relates to a 1.5T dynamic memory unit and array structure based on a resistance variation gate dielectric and a method for operating the same. The 1.5T dynamic memory unit and array structure comprises a transistor, a memory node, a word line, a bit line and a source line, wherein the transistor comprises a source electrode, a drain electrode and a control gate electrode; the memory node is the gate dielectric of the control gate electrode of the transistor and is positioned between the control gate electrode of the transistor and a silicon substrate and used for storing resistance variation states; the word line is connected to the control gate electrode of the transistor; the bit line is connected to the drain electrode of the transistor; the source line is connected to the source electrode of the transistor; a read tube 201 has the effects of gating and limiting current, 202 is a programming part, 203 is the bit line, 204 is the word line of the 201, and 205 is a programming word line; the gate electrode has a high-resistance state and a low-resistance state; the conversion between the high-resistance state and the low-resistance state is reversible; and a certain voltage is applied between the bit line and the word line so as to generate different currents. According to the 1.5T dynamic memory unit and array structure, the problems of difficulty in scaling down and poorer compatibility with the standard CMOS process in a conventional 1T1C (1 Transistor and 1 Capacitor) DRAM (Dynamic Random Access Memory) unit are solved, and the 1.5T dynamic memory unit and array structure can be compatible with a standard logic CMOS HfOx high k metal gate technology.

The invention belongs to the technical field of microelectronics and relates to a metal oxide non-volatile memory technique, in particular to a WOx-based resistance type memory and a preparation method thereof. The WOx-based resistance type memory comprises an upper electrode, a tungsten lower electrode and a WOx-based memory medium which is arranged between the upper electrode and the tungsten lower electrode; the WOx-based memory medium is formed by performing oxidation treatment on a WSI compound covered on the tungsten lower electrode; and x is more than 1 and less than or equal to 3. The resistance type memory has the characteristics of improving the controllability of the process and the reliability of devices, along with relatively low power consumption and high data retention performance.