2t dynamic memory cell and array structure based on resistive gate dielectric and its operation method

Abstract

The invention belongs to the technical field of memory, and relates to a 2T dynamic memory unit based on a resistive gate medium, an array structure and an operation method thereof. The present invention includes a write tube, a read tube, a storage unit, a write word line, a write bit line, a read word line, and a read bit line; the source end of the write tube is connected to the gate of the read tube, and the write tube It has the function of programming, and the gate medium of the reading tube is a storage part; the gate medium has three different states of insulation, high resistance, and low resistance, among which the transition between high resistance and low resistance is reversible, and when reading, it is read into the tube grid. A certain voltage is applied to the electrode and the read word line, and "0" and "1" can be judged according to the voltage change or current value of the read bit line. The invention has the advantages of simple process, low cost, superior effect, low power consumption and high performance, and is compatible with the front end of 32nm High k CMOS logic process.

Description

technical field [0001] The invention belongs to the technical field of memory, and relates to a 2T device and an array structure for an embedded dynamic memory, in particular to a 2T dynamic memory unit and an array structure based on a resistive variable gate medium and an operation method thereof. Background technique [0002] A storage unit of a traditional DRAM typically includes two components: a storage capacitor and an access transistor, forming a 1T1C structure. like figure 1 In the traditional DRAM array structure shown, 100 to 108 are access transistors, 109 to 111 are bit lines, 112 to 114 are word lines, 115 to 117 are parasitic capacitances on bit lines, and 118 to 126 are storage capacitor. Generally, the working process of a traditional DRAM includes, the following takes the operation of the memory cell formed by the access transistor 100 and the storage capacitor 118 as an example: in the write operation phase, the data value is placed on the bit line 109, ...

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Problems solved by technology

This kind of 1T1C structure DRAM relies on storage capacitors to store data, so the storage capacitors must be large enough to ensure the reliability of storage, but the existence of large capacitors not only occupies an area, but also under the development trend of smaller and smaller feature sizes in semiconductor processes , it is very difficult to manufacture large capacitors, which leads to obstacles in physical or process realization

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