A parasitic n-i-p type pin device structure and manufacturing method in a bicmos process

Abstract

The invention discloses a parasitic N-I-P type PIN device structure in a BiCMOS (bipolar complementary metal oxide semiconductor) process. The parasitic N-I-P type PIN device structure is characterized in that an active area is formed above a P type substrate, a P type embedded layer is formed in the active area, a plurality of shallow trench isolators are formed above the P type embedded layer, polycrystalline silicon layers are formed above the shallow trench isolators, emitting areas are formed above the active area, the emitting areas and the polycrystalline silicon layers are alternately arranged, the emitting areas are connected with metal wires in a leading-out manner through contact holes, the P type embedded layer is connected with a metal wire in a leading-out manner through a deep contact hole, and titanium or tin and tungsten are arranged in the deep contact hole. The invention further discloses a manufacturing method of the parasitic N-I-P type PIN device structure in the BiCMOS process. By the aid of the parasitic N-I-P type PIN device structure and the manufacturing method thereof, forward breakover current and the effective area of a PIN device can be increased, and insertion loss of the PIN device is reduced.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a parasitic N-I-P type PIN device structure in a BiCMOS process. The invention also relates to a manufacturing method of a parasitic N-I-P type PIN device structure in a BiCMOS process. Background technique [0002] The conventional Bipolar (insulated gate bipolar transistor) uses a highly doped buried layer in the collector area to reduce the resistance of the collector area, and uses high-concentration and high-energy N-type implantation to connect the buried layer in the collector area to form a collector terminal. (collector pick-up). The low-medium doped collector region is epitaxy on the buried layer of the collector region, the base region is formed on the P-type doped epitaxy, and then the heavily N-type doped polysilicon forms the emitter, and finally the bipolar is completed. Such as figure 1 As shown, the disadvantage of a traditional PIN device structure ...

AI Technical Summary

Problems solved by technology

like figure 1 As shown, the disadvantage of a traditional PIN device structure is that the forward current capability is limited and the insertion loss is large.

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