Through silicon via manufacturing method

Abstract

The invention discloses a through silicon via (TSV, Through Silicon Via) manufacturing method. The method provides a new TSV corrugated metal pipe (CMP) technology. After convex metal is formed according to the prior art to manufacturing the TSV, a polishing step is added, the convex metal in the TSV is polished into a flushed surface and an etch stop layer is removed, so that conductive wires manufactured by the TSV are flushed with the surface, and the semiconductor device yield is improved.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a method for manufacturing a through-silicon via (TSV, Through Silicon Via). Background technique [0002] At present, semiconductor integrated circuit (IC) manufacturing mainly grows and interconnects semiconductor devices on a wafer device surface of a substrate. The semiconductor device is fabricated in the device layer. Taking a metal oxide semiconductor field effect transistor (MOSFET) device as an example, the main structure of the MOSFET device includes: an active region, a source electrode, a drain electrode and a gate electrode, wherein the active region Located in the substrate, the gate is located above the active region, and the active regions on both sides of the gate are respectively implanted with ions to form a source and a drain. There is a conductive channel under the gate, and the gate There is a gate dielectric layer between the electrode ...

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Problems solved by technology

[0015] according to figure 1 When the TSV forms the wire connection, it has gone through the annealing step. During the high-temperature annealing process, due to the different materials of the conductive wire and the metal interconnection layer, the conductive wire will protrude out of the plane, such as protruding from the metal interconnection layer and the lining. On the back surface of the bottom, the height of the protrusion reaches 1 micron to 130 microns, such as image 3 The schematic diagram of the protruding conductive wiring in the TSV shown in the figure will cause a short circuit or open circuit when the subsequent packaging process is performed on the conductive wiring, which will seriously affect the yield of the semiconductor device produced.

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