A method of manufacturing a semiconductor packaging device

Abstract

The invention discloses a manufacture method of a semiconductor package component. A chip load and a pin of a quad flat non-leaded package (QFN) semiconductor package component are not manufactured based on a lead frame structure which is manufactured in advance, while the chip load and the pin which are provided with a step structure are formed by the organic integration of etching, electroplating and chemical plating methods in the process of packaging technology. Seal package is carried out by adopting of plastic package materials, and after the plastic package is finished, the independent chip load and the pin are formed by adopting an etching method or a mechanical grinding method.

Description

technical field [0001] The invention relates to the technical field of manufacturing semiconductor components, in particular to a method for manufacturing a quadrilateral flat no-lead package with high I / O density. Background technique [0002] With the development of electronic products such as mobile phones and notebook computers towards miniaturization, portability, ultra-thinness, multimedia and low-cost requirements for popularization, high-density, high-performance, high-reliability and low-cost packaging forms and Its assembly technology has been developed rapidly. Compared with expensive BGA and other packaging forms, the new packaging technology that has developed rapidly in recent years, that is, the quad flat non-lead QFN (QuadFlatNon-leadPackage) package, has good thermal and electrical properties, small size, low cost and Many advantages such as high productivity have triggered a new revolution in the field of microelectronic packaging technology. [0003] Fi...

AI Technical Summary

Problems solved by technology

[0004] With the improvement of IC integration and the continuous enhancement of functions, the number of I / Os of ICs increases, and the number of I / O pins of corresponding electronic packages also increases accordingly. The pins of the ring are arranged around the chip carrier, which limits the increase in the number of I / Os and cannot meet the needs of high-density ICs with more I / Os.

Even if the traditional QFN package with non-step structure design has multi-turn pins, it cannot effectively lock the plastic packaging material, resulting in low bonding strength between the lead frame and the plastic packaging material, which is easy to cause delamination and even lead-out of the lead frame and plastic packaging material. The feet or the chip carrier fall off, and the moisture cannot be effectively prevented from diffusing into the electronic package along the interface between the lead frame and the plastic packaging material, which seriously affects the reliability of the package.

Even if the traditional QFN package has a stepped structure design, it can only be realized based on single-turn pins or staggered multi-turn pins, and each outer end of all pins must extend to one side of the package body and be exposed to the external environment. In the middle, the moisture is easily diffused into the package, which affects the reliability of the product, and due to the limitation of space, it is impossible to achieve higher density packaging

The chip load and pins of the traditional QFN package must be based on the pre-fabricated lead frame structure, otherwise the chip load and pins cannot complete all the packaging process due to lack of mechanical support and connection

Traditional QFN packages need to paste tape on the back of the lead frame in advance to prevent overflow during the plastic sealing process.

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