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Semiconductor anti-static protection structure

A technology for protecting structures and semiconductors, applied in semiconductor devices, circuits, transistors, etc., can solve problems such as substrate and gate structure burning, and achieve the effect of avoiding burning

Active Publication Date: 2015-11-25
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] However, when the parasitic NPN transistor is turned on, a large drain current will flow from the drain region to the source region, and then flow away from the source region. The large drain current will generate a very high temperature, which may cause The substrate and the gate structure are burned, therefore, how to control the temperature of the substrate between the source region and the drain region is directly related to the performance of the antistatic protection structure

Method used

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  • Semiconductor anti-static protection structure
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  • Semiconductor anti-static protection structure

Examples

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no. 1 example

[0031] The semiconductor anti-static protection structure provided by the first embodiment of the present invention is a FinFET, please refer to Figure 4 , is a three-dimensional schematic diagram of the semiconductor antistatic protection structure of this embodiment, specifically comprising: a semiconductor substrate 100, a fin 105 located on the surface of the semiconductor substrate 100, the fin 105 has an arc-shaped surface, and covers all The gate 130 on the arc-shaped surface of the fin 105, the gate 130 includes a gate oxide layer 131 on the arc-shaped surface of the fin 105 and a gate electrode 132 on the surface of the gate oxide layer 131, The source region 120 and the drain region 110 located at both ends of the fin portion 105 and on the surface of the semiconductor substrate 100, wherein the source region 120, the semiconductor substrate 100, and the gate 130 are grounded, and the drain region 110 and connected to external circuits.

[0032]The semiconductor an...

no. 2 example

[0039] The semiconductor anti-static protection structure provided by the second embodiment of the present invention includes at least two FinFETs. For the specific structure, please refer to Figure 5 and Figure 6 , Figure 5 It is a structural schematic diagram of the top view angle of the semiconductor antistatic protection structure, Figure 6 for along Figure 5 Schematic diagram of the cross-sectional structure of the line AA' in the middle. The semiconductor anti-static protection structure specifically includes: a semiconductor substrate 200, at least two parallel fins 205 located on the surface of the semiconductor substrate 200, the fins 205 are semi-cylindrical, and the semi-cylindrical fins 205 is in contact with the semiconductor substrate 200, covering the gate 230 on the semicircular surface of the semi-cylindrical fin 205, the gate 230 covers all the surfaces of the fin 205 at the same time, the gate 230 includes a gate oxide layer 231 located on the semi-...

no. 3 example

[0046] The semiconductor anti-static protection structure provided by the third embodiment of the present invention includes at least two FinFETs. For the specific structure, please refer to Figure 7 and Figure 8 , Figure 7 It is a structural schematic diagram of the top view angle of the semiconductor antistatic protection structure, Figure 8 for along Figure 7 Schematic diagram of the cross-sectional structure of the middle BB' line. The semiconductor anti-static protection structure specifically includes: a semiconductor substrate 300, at least two parallel fins 305 located on the surface of the semiconductor substrate 300, the fins 305 are semi-cylindrical, and the semi-cylindrical fins The plane surface of 305 is in contact with the semiconductor substrate 300, and the grid 330 covering the semicircular arc surface of the semi-cylindrical fin 305, one grid 330 covers the surface of one fin 305, and the grid 330 includes The gate oxide layer 331 on the semi-arc su...

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Abstract

Provided is a semiconductor antistatic protection structure. The semiconductor antistatic protection structure comprises a semiconductor substrate and a fin portion placed on the surface of the semiconductor substrate grids, wherein the fin portion is provided with arc-shaped surfaces, and P-type foreign ions are mixed in the fin portion and the semiconductor substrate. The semiconductor antistatic protection structure further comprises a grid covering on the arc-shaped surfaces of the fin portion, and a source region and a drain region which are placed at two ends of the fin portion and the surface of the semiconductor substrate, wherein N-type foreign ions are mixed in the source region and the drain region, the source, the semiconductor substrate and the grid are grounded, and the drain region is connected with an external circuit. Due to the facts that the superficial area of the fin portion is larger than area of the substrate between the source region and the drain region in the prior art, drain current flows on unit area is small, the temperature of the fin portion is low, and consequently the fin portion and the grid can not be burnt easily. In addition, the fin portion is provided with the arc-shaped surfaces, the phenomenon of partial large current can not happen, large heat generated partially can not happen, and the fin portion and a grid structure can be prevented from being burnt.

Description

technical field [0001] The invention relates to semiconductor technology, in particular to a semiconductor antistatic protection structure. Background technique [0002] As semiconductor chips are used more and more widely, the electrostatic damage involved in semiconductor chips is also more and more extensive. Usually, the static electricity of the human body wearing nylon products may reach a high voltage of 21000V, and an electrostatic discharge of about 750V can generate sparks, and an electrostatic voltage of only about 10V may damage chips without electrostatic discharge (ESD). There are many designs and applications of anti-static protection circuits, usually including: Gate Grounded NMOS (GGNMOS) protection circuit, diode protection circuit, silicon controlled rectifier (Silicon Controlled Rectifier, SCR) protection circuit, etc. [0003] Among them, the circuit diagram of the gate-grounded N-type field effect transistor (GateGroundedNMOS, GGNMOS) protection circui...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/02
CPCH01L27/0274H01L29/7854
Inventor 甘正浩三重野文健冯军宏
Owner SEMICON MFG INT (SHANGHAI) CORP