LUT (look-up table) structure with MUX (multiplexer) mode and EDA (electronic design automation) optimization method matching with LUT structure

Abstract

The invention discloses an LUT (look-up table) structure with an MUX (multiplexer) mode and an EDA (electronic design automation) optimization method matching with the LUT structure. With minor modification on the basis of a conventional LUT structure, a 4-to-1 MUX originally existing in the conventional LUT structure is utilized for improving logical utilization of MUX realization and reducing circuit delay. A novel strategy that MUX optimization is performed prior to logic optimization is employed in the EDA optimization method matching with MLUT (the LUT structure with the MUX mode); the optimization method is performed based on MUX trees, and includes three steps of MUX tree grouping, MUX tree isomorphism, and MUX tree reconfiguration and mapping. With the optimization method, the MUX trees are mapped to the MLUT to the utmost, and service efficiency of the MLUT is guaranteed. Comparison experiments indicate that occupation on logical resource is greatly reduced, circuit clock frequency is increased, and the MLUT has the advantages of short running time and low memory requirements.

Description

Technical field [0001] The present invention relates to the field of Field Programmable Gate Array (Field Programmable Gate Array, FPGA) and Electronic Design Automation (Electronic Design Automation, EDA) technical fields, in particular to a look-up table structure (MLUT) structure with a multiplexer mode and its Matching EDA optimization method. Background technique [0002] Look-Up Table (LUT) is the basic structure used by most FPGAs to implement combinational logic. Its essence is a random access memory (RAM). At present, 4-input LUTs are mostly used in FPGAs. The 4-input LUT can be regarded as a 16×1 RAM with 4-bit address lines, which can realize all the combinational logic of any 4-variable. [0003] Multiplexer (MUX), as a common component of digital circuit system to construct data path, is widely used in various FPGA designs, such as processors, various bus structures, network switching circuits and data encryption and decryption circuits Wait. According to the testin...

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Problems solved by technology

[0005] At present, FPGA chips based on 4-input LUT structure are the most commonly used. In this type of FPGA chip, a 4-select 1 MUX (MUX4) can be realized by adding 2 LUTs to a MUXF5, such as figure 1 As shown in (a), but in this implementation, only 3 of the 4 input terminals of each LUT are used, and there is a certain waste of logic resources

figure 1 (b) is another implementation of MUX4, compared to figure 1 (a) A MUXF5 is saved, but its disadvantage is that the signal needs to be delayed by two stages of LUT, and the timing performance is poor

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