Six-transistor static random access memory unit

Abstract

The invention provides a six-transistor static random access memory unit which at least comprises a first phase inverter, a second phase inverter and a transmission gate, wherein the first phase inverter is composed of a first PMOS (P-channel Metal Oxide Semiconductor) transistor and a first NMOS (N-channel Metal Oxide Semiconductor) transistor; the second phase inverter is composed of a second PMOS transistor and a second NMOS transistor; the transmission gate is composed of a third NMOS transistor and a fourth NMOS transistor; and a source ohmic contact leading-out structure is adopted by the first PMOS transistor, the first NMOS transistor, the second PMOS transistor and the second NMOS transistor respectively. According to the invention, the heavy doping with same polarity doped in a body area is carried out in a source area of the transistor, so that the ohmic contact between the source area and the body area is realized, a float effect of locally exhausted SOI (Silicon On Insulator) transistor is eliminated, additional technology and territory are not added and the high integration degree of the unit is ensured. The six-transistor static random access memory unit is compatible with a conventional CMOS (Complementary Metal-Oxide-Semiconductor Transistor) technology and is suitable for industrial production.

Description

technical field [0001] The invention belongs to the technical field of memory design and manufacture, in particular to a six-transistor static random access memory unit. Background technique [0002] Memory is divided into flash memory (Flash), dynamic random access memory (DRAM) and static random access memory (SRAM), among which static random access memory (SRAM) has become the first choice for key system storage modules because of its fast read and write and no need for periodic refresh. Such as the cache between the CPU and the main memory. In some high-performance CPUs, the L3 cache composed of SRAM has already accounted for about half of the total chip area. The currently commonly used SRAM unit mainly adopts a six-transistor type, which is composed of a pair of inverters and two pass-gate transistors. The word line controls the switching of the two transfer gate transistors, and the stored data is written or read through the bit line. When designing a six-transisto...

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Problems solved by technology

This will greatly reduce the integration level of the whole chip

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