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Circuit board based on SOPC analog brain waves and method for constructing brain dynamic model

A dynamic model and circuit board technology, applied in electrical digital data processing, special data processing applications, instruments, etc., can solve the problems of multiple hardware components, single dot matrix display display, and reduced board dexterity.

Inactive Publication Date: 2013-11-06
YANSHAN UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] The Chinese patent application number is: 201120522483.3, and the name is: SOPC development platform based on NIOS II system. The application discloses a SOPC development platform based on NIOS II system. There is a defect of single display, and there are too many hardware components involved, which reduces the portability and dexterity of the board

Method used

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  • Circuit board based on SOPC analog brain waves and method for constructing brain dynamic model
  • Circuit board based on SOPC analog brain waves and method for constructing brain dynamic model
  • Circuit board based on SOPC analog brain waves and method for constructing brain dynamic model

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Embodiment Construction

[0022] The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0023] Such as figure 1 As shown, a circuit board based on SOPC simulating EEG, the circuit board includes: FPGA chip, configuration chip, clock source, SDRAM, FLASH, liquid crystal display, JTAG debugging download interface, buttons.

[0024] The FPGA chip uses the EP2C8Q208C8 chip in the Cyclone II series;

[0025] The configuration chip selects EPCS4. The board provides a 50MHz clock source for the system and uses a phase-locked loop PLL to provide a 50MHz clock for SDRAM with a phase difference of -20deg;

[0026] SDRAM uses K4S511632B-TC75 chip;

[0027] FLASH uses JS28F128J3D-75 chip;

[0028] The display screen adopts a 2.4-inch LCD screen without a touch screen, and the resolution is 240×320;

[0029] The buttons respectively control the conversion of the model, the adjustment of the model parameters, and the static displ...

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Abstract

The invention discloses a circuit board based on SOPC (System on a programmable chip) analog brain waves and a method for constructing a brain dynamic model. The circuit board comprises an FPGA (Field Programmable Gate Array) chip, a configuration chip, a clock source, an SDRAM (Synchronous Dynamic Random Access Memory), a FLASH, a display screen, a JTAG (Joint Test Action Group) debugging and downloading interface and buttons. The method comprises the steps as follows: creating a project, naming the project, and creating an SOPC system; establishing a top module of the system; establishing a new project and a corresponding BSP project; compiling a program and arranging a compiler. Through the circuit board and the method, transformation between a single nerve cluster model and a three nerve cluster coupled model, parameter adjustment and static display of a display screen can be realized by the buttons, and brain waves similar normal brain waves and brain waves in epileptic attack are generated and statically displayed by the display screen, thereby providing a foundation for further study on the brain dynamic model, the brain mechanism and hardware controlled by the brain dynamic model.

Description

technical field [0001] The present invention belongs to the intersecting field of digital integrated circuits and neurodynamics, and mainly develops and builds a brain power model based on a System on a programmable chip (SOPC) circuit board to generate brain waves similar to normal and epileptic seizures. In particular, it relates to a circuit board for simulating brain waves based on SOPC and a method for constructing a brain dynamics model. Background technique [0002] With the development of chip manufacturing technology, SOPC technology, that is, programmable system on chip, has become a development direction of embedded system design. It is a more flexible and efficient SOC solution. The second generation of customer-configurable The general-purpose 32-bit RISC soft-core processor, that is, the NIOS II embedded processor system, is currently the more popular SOPC. It is an IP core of FPGA. It is debugged through JTAG. Its biggest feature is that it is a soft core and...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/50
Inventor 刘仙刘会军孙志伟冀俊娥
Owner YANSHAN UNIV
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